blob: de517f8dab9493f2a8492a8aa8ecc59d3d50b1ab [file] [log] [blame]
Thomas Chouc960b132010-04-20 12:49:52 +08001/*
2 * Altera 10/100/1000 triple speed ethernet mac driver
3 *
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <config.h>
12#include <common.h>
13#include <malloc.h>
14#include <net.h>
15#include <command.h>
16#include <asm/cache.h>
17#include <asm/dma-mapping.h>
18#include <miiphy.h>
19#include "altera_tse.h"
20
21/* sgdma debug - print descriptor */
22static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc)
23{
24 debug("SGDMA DEBUG :\n");
25 debug("desc->source : 0x%x \n", (unsigned int)desc->source);
26 debug("desc->destination : 0x%x \n", (unsigned int)desc->destination);
27 debug("desc->next : 0x%x \n", (unsigned int)desc->next);
28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad);
29 debug("desc->destination_pad : 0x%x \n",
30 (unsigned int)desc->destination_pad);
31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad);
32 debug("desc->bytes_to_transfer : 0x%x \n",
33 (unsigned int)desc->bytes_to_transfer);
34 debug("desc->actual_bytes_transferred : 0x%x \n",
35 (unsigned int)desc->actual_bytes_transferred);
36 debug("desc->descriptor_status : 0x%x \n",
37 (unsigned int)desc->descriptor_status);
38 debug("desc->descriptor_control : 0x%x \n",
39 (unsigned int)desc->descriptor_control);
40}
41
42/* This is a generic routine that the SGDMA mode-specific routines
43 * call to populate a descriptor.
44 * arg1 :pointer to first SGDMA descriptor.
45 * arg2 :pointer to next SGDMA descriptor.
46 * arg3 :Address to where data to be written.
47 * arg4 :Address from where data to be read.
48 * arg5 :no of byte to transaction.
49 * arg6 :variable indicating to generate start of packet or not
50 * arg7 :read fixed
51 * arg8 :write fixed
52 * arg9 :read burst
53 * arg10 :write burst
54 * arg11 :atlantic_channel number
55 */
56static void alt_sgdma_construct_descriptor_burst(
57 volatile struct alt_sgdma_descriptor *desc,
58 volatile struct alt_sgdma_descriptor *next,
59 unsigned int *read_addr,
60 unsigned int *write_addr,
61 unsigned short length_or_eop,
62 int generate_eop,
63 int read_fixed,
64 int write_fixed_or_sop,
65 int read_burst,
66 int write_burst,
67 unsigned char atlantic_channel)
68{
69 /*
70 * Mark the "next" descriptor as "not" owned by hardware. This prevents
71 * The SGDMA controller from continuing to process the chain. This is
72 * done as a single IO write to bypass cache, without flushing
73 * the entire descriptor, since only the 8-bit descriptor status must
74 * be flushed.
75 */
76 if (!next)
77 debug("Next descriptor not defined!!\n");
78
79 next->descriptor_control = (next->descriptor_control &
80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK);
81
82 desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF);
83 desc->destination =
84 (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF);
85 desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF);
86 desc->source_pad = 0x0;
87 desc->destination_pad = 0x0;
88 desc->next_pad = 0x0;
89 desc->bytes_to_transfer = length_or_eop;
90 desc->actual_bytes_transferred = 0;
91 desc->descriptor_status = 0x0;
92
93 /* SGDMA burst not currently supported */
94 desc->read_burst = 0;
95 desc->write_burst = 0;
96
97 /*
98 * Set the descriptor control block as follows:
99 * - Set "owned by hardware" bit
100 * - Optionally set "generate EOP" bit
101 * - Optionally set the "read from fixed address" bit
102 * - Optionally set the "write to fixed address bit (which serves
103 * serves as a "generate SOP" control bit in memory-to-stream mode).
104 * - Set the 4-bit atlantic channel, if specified
105 *
106 * Note this step is performed after all other descriptor information
107 * has been filled out so that, if the controller already happens to be
108 * pointing at this descriptor, it will not run (via the "owned by
109 * hardware" bit) until all other descriptor has been set up.
110 */
111
112 desc->descriptor_control =
113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) |
114 (generate_eop ?
115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) |
116 (read_fixed ?
117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) |
118 (write_fixed_or_sop ?
119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) |
120 (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0)
121 );
122}
123
124static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev,
125 volatile struct alt_sgdma_descriptor *desc)
126{
127 unsigned int status;
128 int counter = 0;
129
130 /* Wait for any pending transfers to complete */
131 alt_sgdma_print_desc(desc);
132 status = dev->status;
133
134 counter = 0;
135 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
136 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
137 break;
138 }
139
140 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
141 debug("Timeout waiting sgdma in do sync!\n");
142
143 /*
144 * Clear any (previous) status register information
145 * that might occlude our error checking later.
146 */
147 dev->status = 0xFF;
148
149 /* Point the controller at the descriptor */
150 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
151 debug("next desc in sgdma 0x%x\n",
152 (unsigned int)dev->next_descriptor_pointer);
153
154 /*
155 * Set up SGDMA controller to:
156 * - Disable interrupt generation
157 * - Run once a valid descriptor is written to controller
158 * - Stop on an error with any particular descriptor
159 */
160 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
162
163 /* Wait for the descriptor (chain) to complete */
164 status = dev->status;
165 debug("wait for sgdma....");
166 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK)
167 ;
168 debug("done\n");
169
170 /* Clear Run */
171 dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK));
172
173 /* Get & clear status register contents */
174 status = dev->status;
175 dev->status = 0xFF;
176
177 /* we really should check if the transfer completes properly */
178 debug("tx sgdma status = 0x%x", status);
179 return 0;
180}
181
182static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev,
183 volatile struct alt_sgdma_descriptor *desc)
184{
185 unsigned int status;
186 int counter = 0;
187
188 /* Wait for any pending transfers to complete */
189 alt_sgdma_print_desc(desc);
190 status = dev->status;
191
192 counter = 0;
193 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
194 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
195 break;
196 }
197
198 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
199 debug("Timeout waiting sgdma in do async!\n");
200
201 /*
Joachim Foerster337aff52011-10-25 22:39:54 +0000202 * Clear the RUN bit in the control register. This is needed
203 * to restart the SGDMA engine later on.
204 */
205 dev->control = 0;
206
207 /*
Thomas Chouc960b132010-04-20 12:49:52 +0800208 * Clear any (previous) status register information
209 * that might occlude our error checking later.
210 */
211 dev->status = 0xFF;
212
213 /* Point the controller at the descriptor */
214 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
215
216 /*
217 * Set up SGDMA controller to:
218 * - Disable interrupt generation
219 * - Run once a valid descriptor is written to controller
220 * - Stop on an error with any particular descriptor
221 */
222 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
223 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
224
225 /* we really should check if the transfer completes properly */
226 return 0;
227}
228
229/* u-boot interface */
230static int tse_adjust_link(struct altera_tse_priv *priv)
231{
232 unsigned int refvar;
233
234 refvar = priv->mac_dev->command_config.image;
235
236 if (!(priv->duplexity))
237 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
238 else
239 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
240
241 switch (priv->speed) {
242 case 1000:
243 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
244 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
245 break;
246 case 100:
247 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
248 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
249 break;
250 case 10:
251 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
252 refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
253 break;
254 }
255 priv->mac_dev->command_config.image = refvar;
256
257 return 0;
258}
259
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000260static int tse_eth_send(struct eth_device *dev, void *packet, int length)
Thomas Chouc960b132010-04-20 12:49:52 +0800261{
262 struct altera_tse_priv *priv = dev->priv;
263 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
264 volatile struct alt_sgdma_descriptor *tx_desc =
265 (volatile struct alt_sgdma_descriptor *)priv->tx_desc;
266
267 volatile struct alt_sgdma_descriptor *tx_desc_cur =
268 (volatile struct alt_sgdma_descriptor *)&tx_desc[0];
269
Stefan Kristianssonee04a102011-11-04 02:38:07 +0000270 flush_dcache_range((unsigned long)packet,
271 (unsigned long)packet + length);
Thomas Chouc960b132010-04-20 12:49:52 +0800272 alt_sgdma_construct_descriptor_burst(
273 (volatile struct alt_sgdma_descriptor *)&tx_desc[0],
274 (volatile struct alt_sgdma_descriptor *)&tx_desc[1],
275 (unsigned int *)packet, /* read addr */
276 (unsigned int *)0,
277 length, /* length or EOP ,will change for each tx */
278 0x1, /* gen eop */
279 0x0, /* read fixed */
280 0x1, /* write fixed or sop */
281 0x0, /* read burst */
282 0x0, /* write burst */
283 0x0 /* channel */
284 );
285 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length);
286
287 /* send the packet */
288 debug("sending packet\n");
289 alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur);
290 debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred);
291 return tx_desc_cur->actual_bytes_transferred;
292}
293
294static int tse_eth_rx(struct eth_device *dev)
295{
296 int packet_length = 0;
297 struct altera_tse_priv *priv = dev->priv;
298 volatile struct alt_sgdma_descriptor *rx_desc =
299 (volatile struct alt_sgdma_descriptor *)priv->rx_desc;
300 volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0];
301
302 if (rx_desc_cur->descriptor_status &
303 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
304 debug("got packet\n");
305 packet_length = rx_desc->actual_bytes_transferred;
306 NetReceive(NetRxPackets[0], packet_length);
307
308 /* start descriptor again */
Stefan Kristianssonee04a102011-11-04 02:38:07 +0000309 flush_dcache_range((unsigned long)(NetRxPackets[0]),
310 (unsigned long)(NetRxPackets[0]) + PKTSIZE_ALIGN);
Thomas Chouc960b132010-04-20 12:49:52 +0800311 alt_sgdma_construct_descriptor_burst(
312 (volatile struct alt_sgdma_descriptor *)&rx_desc[0],
313 (volatile struct alt_sgdma_descriptor *)&rx_desc[1],
314 (unsigned int)0x0, /* read addr */
315 (unsigned int *)NetRxPackets[0],
316 0x0, /* length or EOP */
317 0x0, /* gen eop */
318 0x0, /* read fixed */
319 0x0, /* write fixed or sop */
320 0x0, /* read burst */
321 0x0, /* write burst */
322 0x0 /* channel */
323 );
324
325 /* setup the sgdma */
326 alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]);
Joachim Foerster70d52f92011-10-17 05:24:46 +0000327
328 return packet_length;
Thomas Chouc960b132010-04-20 12:49:52 +0800329 }
330
331 return -1;
332}
333
334static void tse_eth_halt(struct eth_device *dev)
335{
336 /* don't do anything! */
337 /* this gets called after each uboot */
338 /* network command. don't need to reset the thing all of the time */
339}
340
341static void tse_eth_reset(struct eth_device *dev)
342{
343 /* stop sgdmas, disable tse receive */
344 struct altera_tse_priv *priv = dev->priv;
345 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
346 volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
347 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
348 int counter;
349 volatile struct alt_sgdma_descriptor *rx_desc =
350 (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0];
351
352 /* clear rx desc & wait for sgdma to complete */
353 rx_desc->descriptor_control = 0;
354 rx_sgdma->control = 0;
355 counter = 0;
356 while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
357 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
358 break;
359 }
360
361 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
362 debug("Timeout waiting for rx sgdma!\n");
Joachim Foerster29095f12011-10-17 05:24:43 +0000363 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
364 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
Thomas Chouc960b132010-04-20 12:49:52 +0800365 }
366
367 counter = 0;
368 tx_sgdma->control = 0;
369 while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
370 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
371 break;
372 }
373
374 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
375 debug("Timeout waiting for tx sgdma!\n");
Joachim Foerster29095f12011-10-17 05:24:43 +0000376 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
377 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
Thomas Chouc960b132010-04-20 12:49:52 +0800378 }
379 /* reset the mac */
380 mac_dev->command_config.bits.transmit_enable = 1;
381 mac_dev->command_config.bits.receive_enable = 1;
382 mac_dev->command_config.bits.software_reset = 1;
383
384 counter = 0;
385 while (mac_dev->command_config.bits.software_reset) {
386 if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR)
387 break;
388 }
389
390 if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR)
391 debug("TSEMAC SW reset bit never cleared!\n");
392}
393
394static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum)
395{
396 volatile struct alt_tse_mac *mac_dev;
397 unsigned int *mdio_regs;
398 unsigned int data;
399 u16 value;
400
401 mac_dev = priv->mac_dev;
402
403 /* set mdio address */
404 mac_dev->mdio_phy1_addr = priv->phyaddr;
405 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
406
407 /* get the data */
408 data = mdio_regs[regnum];
409
410 value = data & 0xffff;
411
412 return value;
413}
414
415static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum,
416 unsigned int value)
417{
418 volatile struct alt_tse_mac *mac_dev;
419 unsigned int *mdio_regs;
420 unsigned int data;
421
422 mac_dev = priv->mac_dev;
423
424 /* set mdio address */
425 mac_dev->mdio_phy1_addr = priv->phyaddr;
426 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
427
428 /* get the data */
429 data = (unsigned int)value;
430
431 mdio_regs[regnum] = data;
432
433 return 0;
434}
435
436/* MDIO access to phy */
437#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
Mike Frysinger5700bb62010-07-27 18:35:08 -0400438static int altera_tse_miiphy_write(const char *devname, unsigned char addr,
Thomas Chouc960b132010-04-20 12:49:52 +0800439 unsigned char reg, unsigned short value)
440{
441 struct eth_device *dev;
442 struct altera_tse_priv *priv;
443 dev = eth_get_dev_by_name(devname);
444 priv = dev->priv;
445
446 tse_mdio_write(priv, (uint) reg, (uint) value);
447
448 return 0;
449}
450
Mike Frysinger5700bb62010-07-27 18:35:08 -0400451static int altera_tse_miiphy_read(const char *devname, unsigned char addr,
Thomas Chouc960b132010-04-20 12:49:52 +0800452 unsigned char reg, unsigned short *value)
453{
454 struct eth_device *dev;
455 struct altera_tse_priv *priv;
456 volatile struct alt_tse_mac *mac_dev;
457 unsigned int *mdio_regs;
458
459 dev = eth_get_dev_by_name(devname);
460 priv = dev->priv;
461
462 mac_dev = priv->mac_dev;
463 mac_dev->mdio_phy1_addr = (int)addr;
464 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
465
466 *value = 0xffff & mdio_regs[reg];
467
468 return 0;
469
470}
471#endif
472
473/*
474 * Also copied from tsec.c
475 */
476/* Parse the status register for link, and then do
477 * auto-negotiation
478 */
479static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv)
480{
481 /*
482 * Wait if the link is up, and autonegotiation is in progress
483 * (ie - we're capable and it's not done)
484 */
485 mii_reg = tse_mdio_read(priv, MIIM_STATUS);
486
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500487 if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE)
488 && !(mii_reg & BMSR_ANEGCOMPLETE)) {
Thomas Chouc960b132010-04-20 12:49:52 +0800489 int i = 0;
490
491 puts("Waiting for PHY auto negotiation to complete");
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500492 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
Thomas Chouc960b132010-04-20 12:49:52 +0800493 /*
494 * Timeout reached ?
495 */
496 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
497 puts(" TIMEOUT !\n");
498 priv->link = 0;
499 return 0;
500 }
501
502 if ((i++ % 1000) == 0)
503 putc('.');
504 udelay(1000); /* 1 ms */
505 mii_reg = tse_mdio_read(priv, MIIM_STATUS);
506 }
507 puts(" done\n");
508 priv->link = 1;
509 udelay(500000); /* another 500 ms (results in faster booting) */
510 } else {
511 if (mii_reg & MIIM_STATUS_LINK) {
512 debug("Link is up\n");
513 priv->link = 1;
514 } else {
515 debug("Link is down\n");
516 priv->link = 0;
517 }
518 }
519
520 return 0;
521}
522
523/* Parse the 88E1011's status register for speed and duplex
524 * information
525 */
526static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv)
527{
528 uint speed;
529
530 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
531
532 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
533 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
534 int i = 0;
535
536 puts("Waiting for PHY realtime link");
537 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
538 /* Timeout reached ? */
539 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
540 puts(" TIMEOUT !\n");
541 priv->link = 0;
542 break;
543 }
544
545 if ((i++ == 1000) == 0) {
546 i = 0;
547 puts(".");
548 }
549 udelay(1000); /* 1 ms */
550 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
551 }
552 puts(" done\n");
553 udelay(500000); /* another 500 ms (results in faster booting) */
554 } else {
555 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
556 priv->link = 1;
557 else
558 priv->link = 0;
559 }
560
561 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
562 priv->duplexity = 1;
563 else
564 priv->duplexity = 0;
565
566 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
567
568 switch (speed) {
569 case MIIM_88E1011_PHYSTAT_GBIT:
570 priv->speed = 1000;
571 debug("PHY Speed is 1000Mbit\n");
572 break;
573 case MIIM_88E1011_PHYSTAT_100:
574 debug("PHY Speed is 100Mbit\n");
575 priv->speed = 100;
576 break;
577 default:
578 debug("PHY Speed is 10Mbit\n");
579 priv->speed = 10;
580 }
581
582 return 0;
583}
584
585static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv)
586{
587 uint mii_data = tse_mdio_read(priv, mii_reg);
588 mii_data &= 0xfff0;
Joachim Foerster15eb1062011-10-25 22:39:57 +0000589 if ((priv->flags >= 1) && (priv->flags <= 4))
590 mii_data |= 0xb;
591 else if (priv->flags == 5)
592 mii_data |= 0x4;
593
Thomas Chouc960b132010-04-20 12:49:52 +0800594 return mii_data;
595}
596
597static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv)
598{
599 uint mii_data = tse_mdio_read(priv, mii_reg);
600 mii_data &= ~0x82;
Joachim Foerster15eb1062011-10-25 22:39:57 +0000601 if ((priv->flags >= 1) && (priv->flags <= 4))
602 mii_data |= 0x82;
603
Thomas Chouc960b132010-04-20 12:49:52 +0800604 return mii_data;
605}
606
607/*
608 * Returns which value to write to the control register.
609 * For 10/100, the value is slightly different
610 */
611static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv)
612{
613 return MIIM_CONTROL_INIT;
614}
615
616/*
617 * PHY & MDIO code
618 * Need to add SGMII stuff
619 *
620 */
621
622static struct phy_info phy_info_M88E1111S = {
623 0x01410cc,
624 "Marvell 88E1111S",
625 4,
626 (struct phy_cmd[]){ /* config */
627 /* Reset and configure the PHY */
628 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
629 {MIIM_88E1111_PHY_EXT_SR, 0x848f,
630 &mii_m88e1111s_setmode_sr},
631 /* Delay RGMII TX and RX */
632 {MIIM_88E1111_PHY_EXT_CR, 0x0cd2,
633 &mii_m88e1111s_setmode_cr},
634 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
635 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
636 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
637 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
638 {miim_end,}
639 },
640 (struct phy_cmd[]){ /* startup */
641 /* Status is read once to clear old link state */
642 {MIIM_STATUS, miim_read, NULL},
643 /* Auto-negotiate */
644 {MIIM_STATUS, miim_read, &mii_parse_sr},
645 /* Read the status */
646 {MIIM_88E1011_PHY_STATUS, miim_read,
647 &mii_parse_88E1011_psr},
648 {miim_end,}
649 },
650 (struct phy_cmd[]){ /* shutdown */
651 {miim_end,}
652 },
653};
654
655/* a generic flavor. */
656static struct phy_info phy_info_generic = {
657 0,
658 "Unknown/Generic PHY",
659 32,
660 (struct phy_cmd[]){ /* config */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500661 {MII_BMCR, BMCR_RESET, NULL},
662 {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL},
Thomas Chouc960b132010-04-20 12:49:52 +0800663 {miim_end,}
664 },
665 (struct phy_cmd[]){ /* startup */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500666 {MII_BMSR, miim_read, NULL},
667 {MII_BMSR, miim_read, &mii_parse_sr},
Thomas Chouc960b132010-04-20 12:49:52 +0800668 {miim_end,}
669 },
670 (struct phy_cmd[]){ /* shutdown */
671 {miim_end,}
672 }
673};
674
675static struct phy_info *phy_info[] = {
676 &phy_info_M88E1111S,
677 NULL
678};
679
680 /* Grab the identifier of the device's PHY, and search through
681 * all of the known PHYs to see if one matches. If so, return
682 * it, if not, return NULL
683 */
684static struct phy_info *get_phy_info(struct eth_device *dev)
685{
686 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
687 uint phy_reg, phy_ID;
688 int i;
689 struct phy_info *theInfo = NULL;
690
691 /* Grab the bits from PHYIR1, and put them in the upper half */
692 phy_reg = tse_mdio_read(priv, MIIM_PHYIR1);
693 phy_ID = (phy_reg & 0xffff) << 16;
694
695 /* Grab the bits from PHYIR2, and put them in the lower half */
696 phy_reg = tse_mdio_read(priv, MIIM_PHYIR2);
697 phy_ID |= (phy_reg & 0xffff);
698
699 /* loop through all the known PHY types, and find one that */
700 /* matches the ID we read from the PHY. */
701 for (i = 0; phy_info[i]; i++) {
702 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
703 theInfo = phy_info[i];
704 break;
705 }
706 }
707
708 if (theInfo == NULL) {
709 theInfo = &phy_info_generic;
710 debug("%s: No support for PHY id %x; assuming generic\n",
711 dev->name, phy_ID);
712 } else
713 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
714
715 return theInfo;
716}
717
718/* Execute the given series of commands on the given device's
719 * PHY, running functions as necessary
720 */
721static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd)
722{
723 int i;
724 uint result;
725
726 for (i = 0; cmd->mii_reg != miim_end; i++) {
727 if (cmd->mii_data == miim_read) {
728 result = tse_mdio_read(priv, cmd->mii_reg);
729
730 if (cmd->funct != NULL)
731 (*(cmd->funct)) (result, priv);
732
733 } else {
734 if (cmd->funct != NULL)
735 result = (*(cmd->funct)) (cmd->mii_reg, priv);
736 else
737 result = cmd->mii_data;
738
739 tse_mdio_write(priv, cmd->mii_reg, result);
740
741 }
742 cmd++;
743 }
744}
745
746/* Phy init code */
747static int init_phy(struct eth_device *dev)
748{
749 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
750 struct phy_info *curphy;
751
752 /* Get the cmd structure corresponding to the attached
753 * PHY */
754 curphy = get_phy_info(dev);
755
756 if (curphy == NULL) {
757 priv->phyinfo = NULL;
758 debug("%s: No PHY found\n", dev->name);
759
760 return 0;
761 } else
762 debug("%s found\n", curphy->name);
763 priv->phyinfo = curphy;
764
765 phy_run_commands(priv, priv->phyinfo->config);
766
767 return 1;
768}
769
Thomas Chou6c7c4442010-04-27 20:15:10 +0800770static int tse_set_mac_address(struct eth_device *dev)
771{
772 struct altera_tse_priv *priv = dev->priv;
773 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
774
775 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n",
776 dev->enetaddr[5], dev->enetaddr[4],
777 dev->enetaddr[3], dev->enetaddr[2],
778 dev->enetaddr[1], dev->enetaddr[0]);
779 mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 |
780 (dev->enetaddr[2]) << 16 |
781 (dev->enetaddr[1]) << 8 | (dev->enetaddr[0]));
782
783 mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 |
784 (dev->enetaddr[4])) & 0xFFFF);
785
786 /* Set the MAC address */
787 mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0;
788 mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1;
789
790 /* Set the MAC address */
791 mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0;
792 mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1;
793
794 /* Set the MAC address */
795 mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0;
796 mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1;
797
798 /* Set the MAC address */
799 mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0;
800 mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1;
801 return 0;
802}
803
Thomas Chouc960b132010-04-20 12:49:52 +0800804static int tse_eth_init(struct eth_device *dev, bd_t * bd)
805{
806 int dat;
807 struct altera_tse_priv *priv = dev->priv;
808 volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
809 volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
810 volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
811 volatile struct alt_sgdma_descriptor *rx_desc_cur =
812 (volatile struct alt_sgdma_descriptor *)&rx_desc[0];
813
814 /* stop controller */
815 debug("Reseting TSE & SGDMAs\n");
816 tse_eth_reset(dev);
817
818 /* start the phy */
819 debug("Configuring PHY\n");
820 phy_run_commands(priv, priv->phyinfo->startup);
821
822 /* need to create sgdma */
823 debug("Configuring tx desc\n");
824 alt_sgdma_construct_descriptor_burst(
825 (volatile struct alt_sgdma_descriptor *)&tx_desc[0],
826 (volatile struct alt_sgdma_descriptor *)&tx_desc[1],
827 (unsigned int *)NULL, /* read addr */
828 (unsigned int *)0,
829 0, /* length or EOP ,will change for each tx */
830 0x1, /* gen eop */
831 0x0, /* read fixed */
832 0x1, /* write fixed or sop */
833 0x0, /* read burst */
834 0x0, /* write burst */
835 0x0 /* channel */
836 );
837 debug("Configuring rx desc\n");
Stefan Kristianssonee04a102011-11-04 02:38:07 +0000838 flush_dcache_range((unsigned long)(NetRxPackets[0]),
839 (unsigned long)(NetRxPackets[0]) + PKTSIZE_ALIGN);
Thomas Chouc960b132010-04-20 12:49:52 +0800840 alt_sgdma_construct_descriptor_burst(
841 (volatile struct alt_sgdma_descriptor *)&rx_desc[0],
842 (volatile struct alt_sgdma_descriptor *)&rx_desc[1],
843 (unsigned int)0x0, /* read addr */
844 (unsigned int *)NetRxPackets[0],
845 0x0, /* length or EOP */
846 0x0, /* gen eop */
847 0x0, /* read fixed */
848 0x0, /* write fixed or sop */
849 0x0, /* read burst */
850 0x0, /* write burst */
851 0x0 /* channel */
852 );
853 /* start rx async transfer */
854 debug("Starting rx sgdma\n");
855 alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur);
856
857 /* start TSE */
858 debug("Configuring TSE Mac\n");
859 /* Initialize MAC registers */
860 mac_dev->max_frame_length = PKTSIZE_ALIGN;
861 mac_dev->rx_almost_empty_threshold = 8;
862 mac_dev->rx_almost_full_threshold = 8;
863 mac_dev->tx_almost_empty_threshold = 8;
864 mac_dev->tx_almost_full_threshold = 3;
865 mac_dev->tx_sel_empty_threshold =
866 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
867 mac_dev->tx_sel_full_threshold = 0;
868 mac_dev->rx_sel_empty_threshold =
869 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
870 mac_dev->rx_sel_full_threshold = 0;
871
872 /* NO Shift */
873 mac_dev->rx_cmd_stat.bits.rx_shift16 = 0;
874 mac_dev->tx_cmd_stat.bits.tx_shift16 = 0;
875
876 /* enable MAC */
877 dat = 0;
878 dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
879
880 mac_dev->command_config.image = dat;
881
Thomas Chouc960b132010-04-20 12:49:52 +0800882 /* configure the TSE core */
883 /* -- output clocks, */
884 /* -- and later config stuff for SGMII */
885 if (priv->link) {
886 debug("Adjusting TSE to link speed\n");
887 tse_adjust_link(priv);
888 }
889
890 return priv->link ? 0 : -1;
891}
892
893/* TSE init code */
894int altera_tse_initialize(u8 dev_num, int mac_base,
Joachim Foersterb962ac72011-10-17 05:24:44 +0000895 int sgdma_rx_base, int sgdma_tx_base,
896 u32 sgdma_desc_base, u32 sgdma_desc_size)
Thomas Chouc960b132010-04-20 12:49:52 +0800897{
898 struct altera_tse_priv *priv;
899 struct eth_device *dev;
900 struct alt_sgdma_descriptor *rx_desc;
901 struct alt_sgdma_descriptor *tx_desc;
902 unsigned long dma_handle;
903
904 dev = (struct eth_device *)malloc(sizeof *dev);
905
906 if (NULL == dev)
907 return 0;
908
909 memset(dev, 0, sizeof *dev);
910
911 priv = malloc(sizeof(*priv));
912
913 if (!priv) {
914 free(dev);
915 return 0;
916 }
Joachim Foersterb962ac72011-10-17 05:24:44 +0000917 if (sgdma_desc_size) {
918 if (sgdma_desc_size < (sizeof(*tx_desc) * (3 + PKTBUFSRX))) {
919 printf("ALTERA_TSE-%hu: "
920 "descriptor memory is too small\n", dev_num);
921 free(priv);
922 free(dev);
923 return 0;
924 }
925 tx_desc = (struct alt_sgdma_descriptor *)sgdma_desc_base;
926 } else {
927 tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX),
928 &dma_handle);
929 }
930
Thomas Chouc960b132010-04-20 12:49:52 +0800931 rx_desc = tx_desc + 2;
932 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc);
933 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc);
934
935 if (!tx_desc) {
936 free(priv);
937 free(dev);
938 return 0;
939 }
940 memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1));
941 memset(tx_desc, 0, (sizeof *tx_desc) * 2);
942
943 /* initialize tse priv */
944 priv->mac_dev = (volatile struct alt_tse_mac *)mac_base;
945 priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base;
946 priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base;
947 priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR;
948 priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS;
949 priv->rx_desc = rx_desc;
950 priv->tx_desc = tx_desc;
951
952 /* init eth structure */
953 dev->priv = priv;
954 dev->init = tse_eth_init;
955 dev->halt = tse_eth_halt;
956 dev->send = tse_eth_send;
957 dev->recv = tse_eth_rx;
Thomas Chou6c7c4442010-04-27 20:15:10 +0800958 dev->write_hwaddr = tse_set_mac_address;
Thomas Chouc960b132010-04-20 12:49:52 +0800959 sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num);
960
961 eth_register(dev);
962
963#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
964 miiphy_register(dev->name, altera_tse_miiphy_read,
965 altera_tse_miiphy_write);
966#endif
967
968 init_phy(dev);
969
970 return 1;
971}