blob: 1003bf61341bd142a0c54d31cbecb337c9812613 [file] [log] [blame]
Kumar Galaff4681c2008-01-17 01:25:33 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
Kumar Galaf69766e2008-01-30 14:55:14 -060030 SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
Kumar Galaff4681c2008-01-17 01:25:33 -060031 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
32 0, 1, BOOKE_PAGESZ_1M, 1),
33
34 #if defined(CFG_FLASH_PORT_WIDTH_16)
35 SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
36 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
37 0, 2, BOOKE_PAGESZ_4M, 1),
38 SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 3, BOOKE_PAGESZ_4M, 1),
41 #else
42 SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
43 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
44 0, 2, BOOKE_PAGESZ_16M, 1),
45 #endif
46
47 #if !defined(CONFIG_SPD_EEPROM)
48 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
49 MAS3_SX|MAS3_SW|MAS3_SR, 0,
50 0, 4, BOOKE_PAGESZ_64M, 1),
51
52 SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
53 MAS3_SX|MAS3_SW|MAS3_SR, 0,
54 0, 5, BOOKE_PAGESZ_64M, 1),
55 #endif
56
57 SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
58 #if defined(CONFIG_RAM_AS_FLASH)
59 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60 #else
61 MAS3_SX|MAS3_SW|MAS3_SR, 0,
62 #endif
63 0, 6, BOOKE_PAGESZ_64M, 1),
64
65 SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
66 MAS3_SX|MAS3_SW|MAS3_SR, 0,
67 0, 7, BOOKE_PAGESZ_16K, 1),
68
69 SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71 0, 8, BOOKE_PAGESZ_256M, 1),
72
73 SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
74 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 0, 9, BOOKE_PAGESZ_16K, 1),
76};
77
78int num_tlb_entries = ARRAY_SIZE(tlb_table);