wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <malloc.h> |
| 26 | #include <commproc.h> |
| 27 | #include <net.h> |
| 28 | #include <command.h> |
| 29 | |
| 30 | #undef ET_DEBUG |
| 31 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 32 | #if (CONFIG_COMMANDS & CFG_CMD_NET) && \ |
| 33 | (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) |
| 34 | |
| 35 | /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ |
| 36 | #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) |
| 37 | #define CONFIG_ETHER_ON_FEC1 1 |
| 38 | #endif |
| 39 | |
| 40 | /* define WANT_MII when MII support is required */ |
| 41 | #if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) |
| 42 | #define WANT_MII |
| 43 | #else |
| 44 | #undef WANT_MII |
| 45 | #endif |
| 46 | |
| 47 | #if defined(WANT_MII) |
| 48 | #include <miiphy.h> |
| 49 | #endif |
| 50 | |
| 51 | #if defined(CONFIG_RMII) && !defined(WANT_MII) |
| 52 | #error RMII support is unusable without a working PHY. |
| 53 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 54 | |
| 55 | #ifdef CFG_DISCOVER_PHY |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 56 | static int mii_discover_phy(struct eth_device *dev); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 57 | #endif |
| 58 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 59 | static struct ether_fcc_info_s |
| 60 | { |
| 61 | int ether_index; |
| 62 | int fecp_offset; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 63 | int phy_addr; |
| 64 | int actual_phy_addr; |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 65 | int initialized; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 66 | } |
| 67 | ether_fcc_info[] = { |
| 68 | #if defined(CONFIG_ETHER_ON_FEC1) |
| 69 | { |
| 70 | 0, |
| 71 | offsetof(immap_t, im_cpm.cp_fec1), |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 72 | #if defined(CONFIG_FEC1_PHY) |
| 73 | CONFIG_FEC1_PHY, |
| 74 | #else |
| 75 | -1, /* discover */ |
| 76 | #endif |
| 77 | -1, |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 78 | 0, |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 79 | |
| 80 | }, |
| 81 | #endif |
| 82 | #if defined(CONFIG_ETHER_ON_FEC2) |
| 83 | { |
| 84 | 1, |
| 85 | offsetof(immap_t, im_cpm.cp_fec2), |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 86 | #if defined(CONFIG_FEC2_PHY) |
| 87 | CONFIG_FEC2_PHY, |
| 88 | #else |
| 89 | -1, |
| 90 | #endif |
| 91 | -1, |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 92 | 0, |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 93 | }, |
| 94 | #endif |
| 95 | }; |
| 96 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 97 | /* Ethernet Transmit and Receive Buffers */ |
| 98 | #define DBUF_LENGTH 1520 |
| 99 | |
| 100 | #define TX_BUF_CNT 2 |
| 101 | |
| 102 | #define TOUT_LOOP 100 |
| 103 | |
| 104 | #define PKT_MAXBUF_SIZE 1518 |
| 105 | #define PKT_MINBUF_SIZE 64 |
| 106 | #define PKT_MAXBLR_SIZE 1520 |
| 107 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 108 | #ifdef __GNUC__ |
| 109 | static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8))); |
| 110 | #else |
| 111 | #error txbuf must be aligned. |
| 112 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 113 | |
| 114 | static uint rxIdx; /* index of the current RX buffer */ |
| 115 | static uint txIdx; /* index of the current TX buffer */ |
| 116 | |
| 117 | /* |
| 118 | * FEC Ethernet Tx and Rx buffer descriptors allocated at the |
| 119 | * immr->udata_bd address on Dual-Port RAM |
| 120 | * Provide for Double Buffering |
| 121 | */ |
| 122 | |
| 123 | typedef volatile struct CommonBufferDescriptor { |
| 124 | cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ |
| 125 | cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ |
| 126 | } RTXBD; |
| 127 | |
| 128 | static RTXBD *rtx = NULL; |
| 129 | |
| 130 | static int fec_send(struct eth_device* dev, volatile void *packet, int length); |
| 131 | static int fec_recv(struct eth_device* dev); |
| 132 | static int fec_init(struct eth_device* dev, bd_t * bd); |
| 133 | static void fec_halt(struct eth_device* dev); |
| 134 | |
| 135 | int fec_initialize(bd_t *bis) |
| 136 | { |
| 137 | struct eth_device* dev; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 138 | struct ether_fcc_info_s *efis; |
| 139 | int i; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 140 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 141 | for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 142 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 143 | dev = malloc(sizeof(*dev)); |
| 144 | if (dev == NULL) |
| 145 | hang(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 146 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 147 | memset(dev, 0, sizeof(*dev)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 148 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 149 | /* for FEC1 make sure that the name of the interface is the same |
| 150 | as the old one for compatibility reasons */ |
| 151 | if (i == 0) { |
| 152 | sprintf (dev->name, "FEC ETHERNET"); |
| 153 | } else { |
| 154 | sprintf (dev->name, "FEC%d ETHERNET", |
| 155 | ether_fcc_info[i].ether_index + 1); |
| 156 | } |
| 157 | |
| 158 | efis = ðer_fcc_info[i]; |
| 159 | |
| 160 | /* |
| 161 | * reset actual phy addr |
| 162 | */ |
| 163 | efis->actual_phy_addr = -1; |
| 164 | |
| 165 | dev->priv = efis; |
| 166 | dev->init = fec_init; |
| 167 | dev->halt = fec_halt; |
| 168 | dev->send = fec_send; |
| 169 | dev->recv = fec_recv; |
| 170 | |
| 171 | eth_register(dev); |
| 172 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 173 | return 1; |
| 174 | } |
| 175 | |
| 176 | static int fec_send(struct eth_device* dev, volatile void *packet, int length) |
| 177 | { |
| 178 | int j, rc; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 179 | struct ether_fcc_info_s *efis = dev->priv; |
| 180 | volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 181 | |
| 182 | /* section 16.9.23.3 |
| 183 | * Wait for ready |
| 184 | */ |
| 185 | j = 0; |
| 186 | while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { |
| 187 | udelay(1); |
| 188 | j++; |
| 189 | } |
| 190 | if (j>=TOUT_LOOP) { |
| 191 | printf("TX not ready\n"); |
| 192 | } |
| 193 | |
| 194 | rtx->txbd[txIdx].cbd_bufaddr = (uint)packet; |
| 195 | rtx->txbd[txIdx].cbd_datlen = length; |
| 196 | rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; |
| 197 | __asm__ ("eieio"); |
| 198 | |
| 199 | /* Activate transmit Buffer Descriptor polling */ |
| 200 | fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ |
| 201 | |
| 202 | j = 0; |
| 203 | while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) { |
| 204 | #if defined(CONFIG_ICU862) |
| 205 | udelay(10); |
| 206 | #else |
| 207 | udelay(1); |
| 208 | #endif |
| 209 | j++; |
| 210 | } |
| 211 | if (j>=TOUT_LOOP) { |
| 212 | printf("TX timeout\n"); |
| 213 | } |
| 214 | #ifdef ET_DEBUG |
| 215 | printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", |
| 216 | __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc, |
| 217 | (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2); |
| 218 | #endif |
| 219 | /* return only status bits */; |
| 220 | rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); |
| 221 | |
| 222 | txIdx = (txIdx + 1) % TX_BUF_CNT; |
| 223 | |
| 224 | return rc; |
| 225 | } |
| 226 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 227 | static int fec_recv (struct eth_device *dev) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 228 | { |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 229 | struct ether_fcc_info_s *efis = dev->priv; |
| 230 | volatile fec_t *fecp = |
| 231 | (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 232 | int length; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 233 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 234 | for (;;) { |
| 235 | /* section 16.9.23.2 */ |
| 236 | if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { |
| 237 | length = -1; |
| 238 | break; /* nothing received - leave for() loop */ |
| 239 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 240 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 241 | length = rtx->rxbd[rxIdx].cbd_datlen; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 242 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 243 | if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 244 | #ifdef ET_DEBUG |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 245 | printf ("%s[%d] err: %x\n", |
| 246 | __FUNCTION__, __LINE__, |
| 247 | rtx->rxbd[rxIdx].cbd_sc); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 248 | #endif |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 249 | } else { |
| 250 | volatile uchar *rx = NetRxPackets[rxIdx]; |
| 251 | |
| 252 | length -= 4; |
| 253 | |
| 254 | #if (CONFIG_COMMANDS & CFG_CMD_CDP) |
| 255 | if ((rx[0] & 1) != 0 |
| 256 | && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 |
| 257 | && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) |
| 258 | rx = NULL; |
| 259 | #endif |
| 260 | /* |
| 261 | * Pass the packet up to the protocol layers. |
| 262 | */ |
| 263 | if (rx != NULL) |
| 264 | NetReceive (rx, length); |
| 265 | } |
| 266 | |
| 267 | /* Give the buffer back to the FEC. */ |
| 268 | rtx->rxbd[rxIdx].cbd_datlen = 0; |
| 269 | |
| 270 | /* wrap around buffer index when necessary */ |
| 271 | if ((rxIdx + 1) >= PKTBUFSRX) { |
| 272 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc = |
| 273 | (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); |
| 274 | rxIdx = 0; |
| 275 | } else { |
| 276 | rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; |
| 277 | rxIdx++; |
| 278 | } |
| 279 | |
| 280 | __asm__ ("eieio"); |
| 281 | |
| 282 | /* Try to fill Buffer Descriptors */ |
| 283 | fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 284 | } |
| 285 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 286 | return length; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | /************************************************************** |
| 290 | * |
| 291 | * FEC Ethernet Initialization Routine |
| 292 | * |
| 293 | *************************************************************/ |
| 294 | |
| 295 | #define FEC_ECNTRL_PINMUX 0x00000004 |
| 296 | #define FEC_ECNTRL_ETHER_EN 0x00000002 |
| 297 | #define FEC_ECNTRL_RESET 0x00000001 |
| 298 | |
| 299 | #define FEC_RCNTRL_BC_REJ 0x00000010 |
| 300 | #define FEC_RCNTRL_PROM 0x00000008 |
| 301 | #define FEC_RCNTRL_MII_MODE 0x00000004 |
| 302 | #define FEC_RCNTRL_DRT 0x00000002 |
| 303 | #define FEC_RCNTRL_LOOP 0x00000001 |
| 304 | |
| 305 | #define FEC_TCNTRL_FDEN 0x00000004 |
| 306 | #define FEC_TCNTRL_HBC 0x00000002 |
| 307 | #define FEC_TCNTRL_GTS 0x00000001 |
| 308 | |
| 309 | #define FEC_RESET_DELAY 50 |
| 310 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 311 | #if defined(CONFIG_RMII) |
| 312 | |
| 313 | static inline void fec_10Mbps(struct eth_device *dev) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 314 | { |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 315 | struct ether_fcc_info_s *efis = dev->priv; |
| 316 | int fecidx = efis->ether_index; |
| 317 | uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 318 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 319 | if ((unsigned int)fecidx >= 2) |
| 320 | hang(); |
| 321 | |
| 322 | ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask; |
| 323 | } |
| 324 | |
| 325 | static inline void fec_100Mbps(struct eth_device *dev) |
| 326 | { |
| 327 | struct ether_fcc_info_s *efis = dev->priv; |
| 328 | int fecidx = efis->ether_index; |
| 329 | uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; |
| 330 | |
| 331 | if ((unsigned int)fecidx >= 2) |
| 332 | hang(); |
| 333 | |
| 334 | ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask; |
| 335 | } |
| 336 | |
| 337 | #endif |
| 338 | |
| 339 | static inline void fec_full_duplex(struct eth_device *dev) |
| 340 | { |
| 341 | struct ether_fcc_info_s *efis = dev->priv; |
| 342 | volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); |
| 343 | |
| 344 | fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT; |
| 345 | fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */ |
| 346 | } |
| 347 | |
| 348 | static inline void fec_half_duplex(struct eth_device *dev) |
| 349 | { |
| 350 | struct ether_fcc_info_s *efis = dev->priv; |
| 351 | volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); |
| 352 | |
| 353 | fecp->fec_r_cntrl |= FEC_RCNTRL_DRT; |
| 354 | fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */ |
| 355 | } |
| 356 | |
| 357 | static void fec_pin_init(int fecidx) |
| 358 | { |
| 359 | DECLARE_GLOBAL_DATA_PTR; |
| 360 | bd_t *bd = gd->bd; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 361 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 362 | volatile fec_t *fecp; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 363 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 364 | /* |
| 365 | * only two FECs please |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 366 | */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 367 | if ((unsigned int)fecidx >= 2) |
| 368 | hang(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 369 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 370 | if (fecidx == 0) |
| 371 | fecp = &immr->im_cpm.cp_fec1; |
| 372 | else |
| 373 | fecp = &immr->im_cpm.cp_fec2; |
| 374 | |
| 375 | /* |
| 376 | * Set MII speed to 2.5 MHz or slightly below. |
| 377 | * * According to the MPC860T (Rev. D) Fast ethernet controller user |
| 378 | * * manual (6.2.14), |
| 379 | * * the MII management interface clock must be less than or equal |
| 380 | * * to 2.5 MHz. |
| 381 | * * This MDC frequency is equal to system clock / (2 * MII_SPEED). |
| 382 | * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. |
| 383 | */ |
| 384 | fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1; |
| 385 | |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 386 | #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) |
| 387 | /* our PHYs are the limit at 2.5 MHz */ |
| 388 | fecp->fec_mii_speed <<= 1; |
| 389 | #endif |
| 390 | |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 391 | #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 392 | /* use MDC for MII */ |
| 393 | immr->im_ioport.iop_pdpar |= 0x0080; |
| 394 | immr->im_ioport.iop_pddir &= ~0x0080; |
| 395 | #endif |
| 396 | |
| 397 | if (fecidx == 0) { |
| 398 | #if defined(CONFIG_ETHER_ON_FEC1) |
| 399 | |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 400 | #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 401 | |
| 402 | #if !defined(CONFIG_RMII) |
| 403 | |
| 404 | immr->im_ioport.iop_papar |= 0xf830; |
| 405 | immr->im_ioport.iop_padir |= 0x0830; |
| 406 | immr->im_ioport.iop_padir &= ~0xf000; |
| 407 | |
| 408 | immr->im_cpm.cp_pbpar |= 0x00001001; |
| 409 | immr->im_cpm.cp_pbdir &= ~0x00001001; |
| 410 | |
| 411 | immr->im_ioport.iop_pcpar |= 0x000c; |
| 412 | immr->im_ioport.iop_pcdir &= ~0x000c; |
| 413 | |
| 414 | immr->im_cpm.cp_pepar |= 0x00000003; |
| 415 | immr->im_cpm.cp_pedir |= 0x00000003; |
| 416 | immr->im_cpm.cp_peso &= ~0x00000003; |
| 417 | |
| 418 | immr->im_cpm.cp_cptr &= ~0x00000100; |
| 419 | |
| 420 | #else |
| 421 | |
| 422 | #if !defined(CONFIG_FEC1_PHY_NORXERR) |
| 423 | immr->im_ioport.iop_papar |= 0x1000; |
| 424 | immr->im_ioport.iop_padir &= ~0x1000; |
| 425 | #endif |
| 426 | immr->im_ioport.iop_papar |= 0xe810; |
| 427 | immr->im_ioport.iop_padir |= 0x0810; |
| 428 | immr->im_ioport.iop_padir &= ~0xe000; |
| 429 | |
| 430 | immr->im_cpm.cp_pbpar |= 0x00000001; |
| 431 | immr->im_cpm.cp_pbdir &= ~0x00000001; |
| 432 | |
| 433 | immr->im_cpm.cp_cptr |= 0x00000100; |
| 434 | immr->im_cpm.cp_cptr &= ~0x00000050; |
| 435 | |
| 436 | #endif /* !CONFIG_RMII */ |
| 437 | |
| 438 | #elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210) |
| 439 | /* |
| 440 | * Configure all of port D for MII. |
| 441 | */ |
| 442 | immr->im_ioport.iop_pdpar = 0x1fff; |
| 443 | |
| 444 | /* |
| 445 | * Bits moved from Rev. D onward |
| 446 | */ |
| 447 | if ((get_immr(0) & 0xffff) < 0x0501) |
| 448 | immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */ |
| 449 | else |
| 450 | immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */ |
| 451 | #else |
| 452 | /* |
| 453 | * Configure port A for MII. |
| 454 | */ |
| 455 | |
| 456 | #if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY) |
| 457 | |
| 458 | /* |
| 459 | * On the ICU862 board the MII-MDC pin is routed to PD8 pin |
| 460 | * * of CPU, so for this board we need to configure Utopia and |
| 461 | * * enable PD8 to MII-MDC function |
| 462 | */ |
| 463 | immr->im_ioport.iop_pdpar |= 0x4080; |
| 464 | #endif |
| 465 | |
| 466 | /* |
| 467 | * Has Utopia been configured? |
| 468 | */ |
| 469 | if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) { |
| 470 | /* |
| 471 | * YES - Use MUXED mode for UTOPIA bus. |
| 472 | * This frees Port A for use by MII (see 862UM table 41-6). |
| 473 | */ |
| 474 | immr->im_ioport.utmode &= ~0x80; |
| 475 | } else { |
| 476 | /* |
| 477 | * NO - set SPLIT mode for UTOPIA bus. |
| 478 | * |
| 479 | * This doesn't really effect UTOPIA (which isn't |
| 480 | * enabled anyway) but just tells the 862 |
| 481 | * to use port A for MII (see 862UM table 41-6). |
| 482 | */ |
| 483 | immr->im_ioport.utmode |= 0x80; |
| 484 | } |
| 485 | #endif /* !defined(CONFIG_ICU862) */ |
| 486 | |
| 487 | #endif /* CONFIG_ETHER_ON_FEC1 */ |
| 488 | } else if (fecidx == 1) { |
| 489 | |
| 490 | #if defined(CONFIG_ETHER_ON_FEC2) |
| 491 | |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 492 | #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 493 | |
| 494 | #if !defined(CONFIG_RMII) |
| 495 | |
| 496 | #warning this configuration is not tested; please report if it works |
| 497 | immr->im_cpm.cp_pepar |= 0x0003fffc; |
| 498 | immr->im_cpm.cp_pedir |= 0x0003fffc; |
| 499 | immr->im_cpm.cp_peso &= ~0x000087fc; |
| 500 | immr->im_cpm.cp_peso |= 0x00037800; |
| 501 | |
| 502 | immr->im_cpm.cp_cptr &= ~0x00000080; |
| 503 | #else |
| 504 | |
| 505 | #if !defined(CONFIG_FEC2_PHY_NORXERR) |
| 506 | immr->im_cpm.cp_pepar |= 0x00000010; |
| 507 | immr->im_cpm.cp_pedir |= 0x00000010; |
| 508 | immr->im_cpm.cp_peso &= ~0x00000010; |
| 509 | #endif |
| 510 | immr->im_cpm.cp_pepar |= 0x00039620; |
| 511 | immr->im_cpm.cp_pedir |= 0x00039620; |
| 512 | immr->im_cpm.cp_peso |= 0x00031000; |
| 513 | immr->im_cpm.cp_peso &= ~0x00008620; |
| 514 | |
| 515 | immr->im_cpm.cp_cptr |= 0x00000080; |
| 516 | immr->im_cpm.cp_cptr &= ~0x00000028; |
| 517 | #endif /* CONFIG_RMII */ |
| 518 | |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 519 | #endif /* CONFIG_MPC885_FAMILY */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 520 | |
| 521 | #endif /* CONFIG_ETHER_ON_FEC2 */ |
| 522 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 523 | } |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 524 | } |
| 525 | |
| 526 | static int fec_init (struct eth_device *dev, bd_t * bd) |
| 527 | { |
| 528 | struct ether_fcc_info_s *efis = dev->priv; |
| 529 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 530 | volatile fec_t *fecp = |
| 531 | (volatile fec_t *) (CFG_IMMR + efis->fecp_offset); |
| 532 | int i; |
| 533 | |
| 534 | if (efis->ether_index == 0) { |
| 535 | #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 536 | #if defined(CONFIG_MPC885ADS) |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 537 | *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); |
| 538 | #else |
| 539 | /* configure FADS for fast (FEC) ethernet, half-duplex */ |
| 540 | /* The LXT970 needs about 50ms to recover from reset, so |
| 541 | * wait for it by discovering the PHY before leaving eth_init(). |
| 542 | */ |
| 543 | { |
| 544 | volatile uint *bcsr4 = (volatile uint *) BCSR4; |
| 545 | |
| 546 | *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1)) |
| 547 | | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | |
| 548 | BCSR4_FETHRST); |
| 549 | |
| 550 | /* reset the LXT970 PHY */ |
| 551 | *bcsr4 &= ~BCSR4_FETHRST; |
| 552 | udelay (10); |
| 553 | *bcsr4 |= BCSR4_FETHRST; |
| 554 | udelay (10); |
| 555 | } |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 556 | #endif /* CONFIG_MPC885ADS */ |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 557 | #endif /* CONFIG_FADS */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 558 | } |
| 559 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 560 | /* Whack a reset. |
| 561 | * A delay is required between a reset of the FEC block and |
| 562 | * initialization of other FEC registers because the reset takes |
| 563 | * some time to complete. If you don't delay, subsequent writes |
| 564 | * to FEC registers might get killed by the reset routine which is |
| 565 | * still in progress. |
| 566 | */ |
| 567 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; |
| 568 | for (i = 0; |
| 569 | (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); |
| 570 | ++i) { |
| 571 | udelay (1); |
| 572 | } |
| 573 | if (i == FEC_RESET_DELAY) { |
| 574 | printf ("FEC_RESET_DELAY timeout\n"); |
| 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | /* We use strictly polling mode only |
| 579 | */ |
| 580 | fecp->fec_imask = 0; |
| 581 | |
| 582 | /* Clear any pending interrupt |
| 583 | */ |
| 584 | fecp->fec_ievent = 0xffc0; |
| 585 | |
| 586 | /* No need to set the IVEC register */ |
| 587 | |
| 588 | /* Set station address |
| 589 | */ |
| 590 | #define ea eth_get_dev()->enetaddr |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 591 | fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); |
| 592 | fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 593 | #undef ea |
| 594 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 595 | #if (CONFIG_COMMANDS & CFG_CMD_CDP) |
| 596 | /* |
| 597 | * Turn on multicast address hash table |
| 598 | */ |
| 599 | fecp->fec_hash_table_high = 0xffffffff; |
| 600 | fecp->fec_hash_table_low = 0xffffffff; |
| 601 | #else |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 602 | /* Clear multicast address hash table |
| 603 | */ |
| 604 | fecp->fec_hash_table_high = 0; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 605 | fecp->fec_hash_table_low = 0; |
| 606 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 607 | |
| 608 | /* Set maximum receive buffer size. |
| 609 | */ |
| 610 | fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; |
| 611 | |
| 612 | /* Set maximum frame length |
| 613 | */ |
| 614 | fecp->fec_r_hash = PKT_MAXBUF_SIZE; |
| 615 | |
| 616 | /* |
| 617 | * Setup Buffers and Buffer Desriptors |
| 618 | */ |
| 619 | rxIdx = 0; |
| 620 | txIdx = 0; |
| 621 | |
| 622 | if (!rtx) { |
| 623 | #ifdef CFG_ALLOC_DPRAM |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 624 | rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + |
| 625 | dpram_alloc_align (sizeof (RTXBD), 8)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 626 | #else |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 627 | rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 628 | #endif |
| 629 | } |
| 630 | /* |
| 631 | * Setup Receiver Buffer Descriptors (13.14.24.18) |
| 632 | * Settings: |
| 633 | * Empty, Wrap |
| 634 | */ |
| 635 | for (i = 0; i < PKTBUFSRX; i++) { |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 636 | rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; |
| 637 | rtx->rxbd[i].cbd_datlen = 0; /* Reset */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 638 | rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; |
| 639 | } |
| 640 | rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; |
| 641 | |
| 642 | /* |
| 643 | * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) |
| 644 | * Settings: |
| 645 | * Last, Tx CRC |
| 646 | */ |
| 647 | for (i = 0; i < TX_BUF_CNT; i++) { |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 648 | rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; |
| 649 | rtx->txbd[i].cbd_datlen = 0; /* Reset */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 650 | rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); |
| 651 | } |
| 652 | rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; |
| 653 | |
| 654 | /* Set receive and transmit descriptor base |
| 655 | */ |
| 656 | fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); |
| 657 | fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); |
| 658 | |
| 659 | /* Enable MII mode |
| 660 | */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 661 | #if 0 /* Full duplex mode */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 662 | fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; |
| 663 | fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 664 | #else /* Half duplex mode */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 665 | fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; |
| 666 | fecp->fec_x_cntrl = 0; |
| 667 | #endif |
| 668 | |
| 669 | /* Enable big endian and don't care about SDMA FC. |
| 670 | */ |
| 671 | fecp->fec_fun_code = 0x78000000; |
| 672 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 673 | /* |
| 674 | * Setup the pin configuration of the FEC |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 675 | */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 676 | fec_pin_init (efis->ether_index); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 677 | |
| 678 | rxIdx = 0; |
| 679 | txIdx = 0; |
| 680 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 681 | /* |
| 682 | * Now enable the transmit and receive processing |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 683 | */ |
| 684 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; |
| 685 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 686 | if (efis->phy_addr == -1) { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 687 | #ifdef CFG_DISCOVER_PHY |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 688 | /* |
| 689 | * wait for the PHY to wake up after reset |
| 690 | */ |
| 691 | efis->actual_phy_addr = mii_discover_phy (dev); |
wdenk | 62b4ac9 | 2004-05-05 08:31:53 +0000 | [diff] [blame] | 692 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 693 | if (efis->actual_phy_addr == -1) { |
| 694 | printf ("Unable to discover phy!\n"); |
| 695 | return 0; |
| 696 | } |
wdenk | 62b4ac9 | 2004-05-05 08:31:53 +0000 | [diff] [blame] | 697 | #else |
| 698 | efis->actual_phy_addr = -1; |
| 699 | #endif |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 700 | } else { |
| 701 | efis->actual_phy_addr = efis->phy_addr; |
| 702 | } |
| 703 | #if defined(CONFIG_MII) && defined(CONFIG_RMII) |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 704 | |
| 705 | /* the MII interface is connected to FEC1 |
wdenk | 6e59238 | 2004-04-18 17:39:38 +0000 | [diff] [blame] | 706 | * so for the miiphy_xxx function to work we must |
| 707 | * call mii_init since fec_halt messes the thing up |
| 708 | */ |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 709 | if (efis->ether_index != 0) |
| 710 | mii_init(); |
| 711 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 712 | /* |
| 713 | * adapt the RMII speed to the speed of the phy |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 714 | */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 715 | if (miiphy_speed (efis->actual_phy_addr) == _100BASET) { |
| 716 | fec_100Mbps (dev); |
| 717 | } else { |
| 718 | fec_10Mbps (dev); |
| 719 | } |
| 720 | #endif |
| 721 | |
| 722 | #if defined(CONFIG_MII) |
| 723 | /* |
| 724 | * adapt to the half/full speed settings |
| 725 | */ |
| 726 | if (miiphy_duplex (efis->actual_phy_addr) == FULL) { |
| 727 | fec_full_duplex (dev); |
| 728 | } else { |
| 729 | fec_half_duplex (dev); |
| 730 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 731 | #endif |
| 732 | |
| 733 | /* And last, try to fill Rx Buffer Descriptors */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 734 | fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 735 | |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 736 | efis->initialized = 1; |
| 737 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 738 | return 1; |
| 739 | } |
| 740 | |
| 741 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 742 | static void fec_halt(struct eth_device* dev) |
| 743 | { |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 744 | struct ether_fcc_info_s *efis = dev->priv; |
| 745 | volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset); |
| 746 | int i; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 747 | |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 748 | /* avoid halt if initialized; mii gets stuck otherwise */ |
| 749 | if (!efis->initialized) |
| 750 | return; |
| 751 | |
| 752 | /* Whack a reset. |
| 753 | * A delay is required between a reset of the FEC block and |
| 754 | * initialization of other FEC registers because the reset takes |
| 755 | * some time to complete. If you don't delay, subsequent writes |
| 756 | * to FEC registers might get killed by the reset routine which is |
| 757 | * still in progress. |
| 758 | */ |
| 759 | |
| 760 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; |
| 761 | for (i = 0; |
| 762 | (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); |
| 763 | ++i) { |
| 764 | udelay (1); |
| 765 | } |
| 766 | if (i == FEC_RESET_DELAY) { |
| 767 | printf ("FEC_RESET_DELAY timeout\n"); |
| 768 | return; |
| 769 | } |
| 770 | |
| 771 | efis->initialized = 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 772 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 773 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 774 | #if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 775 | |
| 776 | /* Make MII read/write commands for the FEC. |
| 777 | */ |
| 778 | |
| 779 | #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ |
| 780 | (REG & 0x1f) << 18)) |
| 781 | |
| 782 | #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ |
| 783 | (REG & 0x1f) << 18) | \ |
| 784 | (VAL & 0xffff)) |
| 785 | |
| 786 | /* Interrupt events/masks. |
| 787 | */ |
| 788 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
| 789 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ |
| 790 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ |
| 791 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ |
| 792 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ |
| 793 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ |
| 794 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ |
| 795 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ |
| 796 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ |
| 797 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ |
| 798 | |
| 799 | /* PHY identification |
| 800 | */ |
| 801 | #define PHY_ID_LXT970 0x78100000 /* LXT970 */ |
| 802 | #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ |
| 803 | #define PHY_ID_82555 0x02a80150 /* Intel 82555 */ |
| 804 | #define PHY_ID_QS6612 0x01814400 /* QS6612 */ |
| 805 | #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ |
| 806 | #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ |
| 807 | #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 808 | #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 809 | |
| 810 | /* send command to phy using mii, wait for result */ |
| 811 | static uint |
| 812 | mii_send(uint mii_cmd) |
| 813 | { |
| 814 | uint mii_reply; |
| 815 | volatile fec_t *ep; |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 816 | int cnt; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 817 | |
| 818 | ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec); |
| 819 | |
| 820 | ep->fec_mii_data = mii_cmd; /* command to phy */ |
| 821 | |
| 822 | /* wait for mii complete */ |
wdenk | c26e454 | 2004-04-18 10:13:26 +0000 | [diff] [blame] | 823 | cnt = 0; |
| 824 | while (!(ep->fec_ievent & FEC_ENET_MII)) { |
| 825 | if (++cnt > 1000) { |
| 826 | printf("mii_send STUCK!\n"); |
| 827 | break; |
| 828 | } |
| 829 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 830 | mii_reply = ep->fec_mii_data; /* result from phy */ |
| 831 | ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ |
| 832 | #if 0 |
| 833 | printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", |
| 834 | __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply); |
| 835 | #endif |
| 836 | return (mii_reply & 0xffff); /* data read from phy */ |
| 837 | } |
| 838 | #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ |
| 839 | |
| 840 | #if defined(CFG_DISCOVER_PHY) |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 841 | static int mii_discover_phy(struct eth_device *dev) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 842 | { |
| 843 | #define MAX_PHY_PASSES 11 |
| 844 | uint phyno; |
| 845 | int pass; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 846 | uint phytype; |
| 847 | int phyaddr; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 848 | |
| 849 | phyaddr = -1; /* didn't find a PHY yet */ |
| 850 | for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { |
| 851 | if (pass > 1) { |
| 852 | /* PHY may need more time to recover from reset. |
| 853 | * The LXT970 needs 50ms typical, no maximum is |
| 854 | * specified, so wait 10ms before try again. |
| 855 | * With 11 passes this gives it 100ms to wake up. |
| 856 | */ |
| 857 | udelay(10000); /* wait 10ms */ |
| 858 | } |
| 859 | for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { |
| 860 | phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); |
| 861 | #ifdef ET_DEBUG |
| 862 | printf("PHY type 0x%x pass %d type ", phytype, pass); |
| 863 | #endif |
| 864 | if (phytype != 0xffff) { |
| 865 | phyaddr = phyno; |
| 866 | phytype <<= 16; |
| 867 | phytype |= mii_send(mk_mii_read(phyno, |
| 868 | PHY_PHYIDR2)); |
| 869 | |
| 870 | #ifdef ET_DEBUG |
| 871 | printf("PHY @ 0x%x pass %d type ",phyno,pass); |
| 872 | switch (phytype & 0xfffffff0) { |
| 873 | case PHY_ID_LXT970: |
| 874 | printf("LXT970\n"); |
| 875 | break; |
| 876 | case PHY_ID_LXT971: |
| 877 | printf("LXT971\n"); |
| 878 | break; |
| 879 | case PHY_ID_82555: |
| 880 | printf("82555\n"); |
| 881 | break; |
| 882 | case PHY_ID_QS6612: |
| 883 | printf("QS6612\n"); |
| 884 | break; |
| 885 | case PHY_ID_AMD79C784: |
| 886 | printf("AMD79C784\n"); |
| 887 | break; |
| 888 | case PHY_ID_LSI80225B: |
| 889 | printf("LSI L80225/B\n"); |
| 890 | break; |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 891 | case PHY_ID_DM9161: |
| 892 | printf("Davicom DM9161\n"); |
| 893 | break; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 894 | default: |
| 895 | printf("0x%08x\n", phytype); |
| 896 | break; |
| 897 | } |
| 898 | #endif |
| 899 | } |
| 900 | } |
| 901 | } |
| 902 | if (phyaddr < 0) { |
| 903 | printf("No PHY device found.\n"); |
| 904 | } |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 905 | return phyaddr; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 906 | } |
| 907 | #endif /* CFG_DISCOVER_PHY */ |
| 908 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 909 | #if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 910 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 911 | /**************************************************************************** |
| 912 | * mii_init -- Initialize the MII for MII command without ethernet |
| 913 | * This function is a subset of eth_init |
| 914 | **************************************************************************** |
| 915 | */ |
| 916 | void mii_init (void) |
| 917 | { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 918 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 919 | volatile fec_t *fecp = &(immr->im_cpm.cp_fec); |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 920 | int i, j; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 921 | |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 922 | for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) { |
| 923 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 924 | /* Whack a reset. |
| 925 | * A delay is required between a reset of the FEC block and |
| 926 | * initialization of other FEC registers because the reset takes |
| 927 | * some time to complete. If you don't delay, subsequent writes |
| 928 | * to FEC registers might get killed by the reset routine which is |
| 929 | * still in progress. |
| 930 | */ |
| 931 | |
| 932 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; |
| 933 | for (i = 0; |
| 934 | (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); |
| 935 | ++i) { |
| 936 | udelay (1); |
| 937 | } |
| 938 | if (i == FEC_RESET_DELAY) { |
| 939 | printf ("FEC_RESET_DELAY timeout\n"); |
| 940 | return; |
| 941 | } |
| 942 | |
| 943 | /* We use strictly polling mode only |
| 944 | */ |
| 945 | fecp->fec_imask = 0; |
| 946 | |
| 947 | /* Clear any pending interrupt |
| 948 | */ |
| 949 | fecp->fec_ievent = 0xffc0; |
| 950 | |
wdenk | 1114257 | 2004-06-06 21:35:06 +0000 | [diff] [blame^] | 951 | /* Setup the pin configuration of the FEC(s) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 952 | */ |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 953 | fec_pin_init(ether_fcc_info[i].ether_index); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 954 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 955 | /* Now enable the transmit and receive processing |
| 956 | */ |
| 957 | fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 958 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 959 | } |
wdenk | a6ab4bf | 2004-04-15 21:31:56 +0000 | [diff] [blame] | 960 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 961 | /***************************************************************************** |
| 962 | * Read and write a MII PHY register, routines used by MII Utilities |
| 963 | * |
| 964 | * FIXME: These routines are expected to return 0 on success, but mii_send |
| 965 | * does _not_ return an error code. Maybe 0xFFFF means error, i.e. |
| 966 | * no PHY connected... |
| 967 | * For now always return 0. |
| 968 | * FIXME: These routines only work after calling eth_init() at least once! |
| 969 | * Otherwise they hang in mii_send() !!! Sorry! |
| 970 | *****************************************************************************/ |
| 971 | |
| 972 | int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) |
| 973 | { |
| 974 | short rdreg; /* register working value */ |
| 975 | |
| 976 | #ifdef MII_DEBUG |
| 977 | printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); |
| 978 | #endif |
| 979 | rdreg = mii_send(mk_mii_read(addr, reg)); |
| 980 | |
| 981 | *value = rdreg; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 982 | #ifdef MII_DEBUG |
| 983 | printf ("0x%04x\n", *value); |
| 984 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 985 | return 0; |
| 986 | } |
| 987 | |
| 988 | int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) |
| 989 | { |
| 990 | short rdreg; /* register working value */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 991 | #ifdef MII_DEBUG |
| 992 | printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); |
| 993 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 994 | rdreg = mii_send(mk_mii_write(addr, reg, value)); |
| 995 | |
| 996 | #ifdef MII_DEBUG |
| 997 | printf ("0x%04x\n", value); |
| 998 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 999 | return 0; |
| 1000 | } |
| 1001 | #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/ |
| 1002 | |
| 1003 | #endif /* CFG_CMD_NET, FEC_ENET */ |