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Dave Liu8bd522c2008-01-11 18:48:24 +08001/*
Scott Woode8d3ca82010-08-30 18:04:52 -05002 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
Dave Liu8bd522c2008-01-11 18:48:24 +08003 *
4 * Dave Liu <daveliu@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Dave Liu8bd522c2008-01-11 18:48:24 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Scott Woodf1c574d2010-11-24 13:28:40 +000012#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
13#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
14#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
15#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
16#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018#ifndef CONFIG_SYS_TEXT_BASE
19#define CONFIG_SYS_TEXT_BASE 0xFE000000
Anton Vorontsov2e950042009-11-24 20:12:12 +030020#endif
21
Scott Woodf1c574d2010-11-24 13:28:40 +000022#ifndef CONFIG_SYS_MONITOR_BASE
23#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
24#endif
25
Dave Liu8bd522c2008-01-11 18:48:24 +080026/*
27 * High Level Configuration Options
28 */
29#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050030#define CONFIG_MPC831x 1 /* MPC831x CPU family */
Dave Liu8bd522c2008-01-11 18:48:24 +080031#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
32#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
33
34/*
35 * System Clock Setup
36 */
37#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
38#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
39
40/*
41 * Hardware Reset Configuration Word
42 * if CLKIN is 66.66MHz, then
43 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
44 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_HRCW_LOW (\
Dave Liu8bd522c2008-01-11 18:48:24 +080046 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
47 HRCWL_DDR_TO_SCB_CLK_2X1 |\
48 HRCWL_SVCOD_DIV_2 |\
49 HRCWL_CSB_TO_CLKIN_2X1 |\
50 HRCWL_CORE_TO_CSB_3X1)
Anton Vorontsov2e950042009-11-24 20:12:12 +030051#define CONFIG_SYS_HRCW_HIGH_BASE (\
Dave Liu8bd522c2008-01-11 18:48:24 +080052 HRCWH_PCI_HOST |\
53 HRCWH_PCI1_ARBITER_ENABLE |\
54 HRCWH_CORE_ENABLE |\
Dave Liu8bd522c2008-01-11 18:48:24 +080055 HRCWH_BOOTSEQ_DISABLE |\
56 HRCWH_SW_WATCHDOG_DISABLE |\
Dave Liu8bd522c2008-01-11 18:48:24 +080057 HRCWH_TSEC1M_IN_RGMII |\
58 HRCWH_TSEC2M_IN_RGMII |\
59 HRCWH_BIG_ENDIAN |\
60 HRCWH_LALE_NORMAL)
61
Anton Vorontsov2e950042009-11-24 20:12:12 +030062#ifdef CONFIG_NAND_SPL
63#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_ROM_LOC_NAND_SP_8BIT |\
66 HRCWH_RL_EXT_NAND)
67#else
68#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
69 HRCWH_FROM_0X00000100 |\
70 HRCWH_ROM_LOC_LOCAL_16BIT |\
71 HRCWH_RL_EXT_LEGACY)
72#endif
73
Dave Liu8bd522c2008-01-11 18:48:24 +080074/*
75 * System IO Config
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_SICRH 0x00000000
78#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
Dave Liu8bd522c2008-01-11 18:48:24 +080079
80#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Anton Vorontsovb8b71ff2009-06-10 00:25:36 +040081#define CONFIG_HWCONFIG
Dave Liu8bd522c2008-01-11 18:48:24 +080082
83/*
84 * IMMR new address
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu8bd522c2008-01-11 18:48:24 +080087
88/*
89 * Arbiter Setup
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger6f681b72011-10-11 23:57:11 -050092#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
93#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
Dave Liu8bd522c2008-01-11 18:48:24 +080094
95/*
96 * DDR Setup
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
99#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
101#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Joe Hershberger6f681b72011-10-11 23:57:11 -0500102#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800103 | DDRCDR_PZ_LOZ \
104 | DDRCDR_NZ_LOZ \
105 | DDRCDR_ODT \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500106 | DDRCDR_Q_DRN)
Dave Liu8bd522c2008-01-11 18:48:24 +0800107 /* 0x7b880001 */
108/*
109 * Manually set up DDR parameters
110 * consist of two chips HY5PS12621BFP-C4 from HYNIX
111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_DDR_SIZE 128 /* MB */
113#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger6f681b72011-10-11 23:57:11 -0500114#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500115 | CSCONFIG_ODT_RD_NEVER \
116 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500117 | CSCONFIG_ROW_BIT_13 \
118 | CSCONFIG_COL_BIT_10)
Dave Liu8bd522c2008-01-11 18:48:24 +0800119 /* 0x80010102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500121#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
122 | (0 << TIMING_CFG0_WRT_SHIFT) \
123 | (0 << TIMING_CFG0_RRT_SHIFT) \
124 | (0 << TIMING_CFG0_WWT_SHIFT) \
125 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
126 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
127 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
128 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800129 /* 0x00220802 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500130#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
131 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
132 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
133 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
134 | (6 << TIMING_CFG1_REFREC_SHIFT) \
135 | (2 << TIMING_CFG1_WRREC_SHIFT) \
136 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
137 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800138 /* 0x27256222 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500139#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
140 | (4 << TIMING_CFG2_CPO_SHIFT) \
141 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
142 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
143 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
144 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
145 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800146 /* 0x121048c5 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500147#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
148 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800149 /* 0x03600100 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500150#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800151 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500152 | SDRAM_CFG_DBW_32)
Dave Liu8bd522c2008-01-11 18:48:24 +0800153 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500155#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
156 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800157 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500158#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800159
160/*
161 * Memory test
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
164#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
165#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu8bd522c2008-01-11 18:48:24 +0800166
167/*
168 * The reserved memory
169 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500170#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
171#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu8bd522c2008-01-11 18:48:24 +0800172
173/*
174 * Initial RAM Base Address Setup
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_RAM_LOCK 1
177#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200178#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500179#define CONFIG_SYS_GBL_DATA_OFFSET \
180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu8bd522c2008-01-11 18:48:24 +0800181
182/*
183 * Local Bus Configuration & Clock Setup
184 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500185#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
186#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_LBC_LBCR 0x00040000
Becky Bruce0914f482010-06-17 11:37:18 -0500188#define CONFIG_FSL_ELBC 1
Dave Liu8bd522c2008-01-11 18:48:24 +0800189
190/*
191 * FLASH on the Local Bus
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200194#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Dave Liu8bd522c2008-01-11 18:48:24 +0800196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500198#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
199#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu8bd522c2008-01-11 18:48:24 +0800200
Joe Hershberger6f681b72011-10-11 23:57:11 -0500201 /* Window base at flash base */
202#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500203#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Dave Liu8bd522c2008-01-11 18:48:24 +0800204
Anton Vorontsov2e950042009-11-24 20:12:12 +0300205#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500206 | BR_PS_16 /* 16 bit port */ \
207 | BR_MS_GPCM /* MSEL = GPCM */ \
208 | BR_V) /* valid */
209#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
210 | OR_UPM_XAM \
211 | OR_GPCM_CSNT \
212 | OR_GPCM_ACS_DIV2 \
213 | OR_GPCM_XACS \
214 | OR_GPCM_SCY_15 \
215 | OR_GPCM_TRLX_SET \
216 | OR_GPCM_EHTR_SET \
217 | OR_GPCM_EAD)
Dave Liu8bd522c2008-01-11 18:48:24 +0800218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500220/* 127 64KB sectors and 8 8KB top sectors per device */
221#define CONFIG_SYS_MAX_FLASH_SECT 135
Dave Liu8bd522c2008-01-11 18:48:24 +0800222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#undef CONFIG_SYS_FLASH_CHECKSUM
224#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
225#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu8bd522c2008-01-11 18:48:24 +0800226
227/*
228 * NAND Flash on the Local Bus
229 */
Anton Vorontsov2e950042009-11-24 20:12:12 +0300230
231#ifdef CONFIG_NAND_SPL
232#define CONFIG_SYS_NAND_BASE 0xFFF00000
233#else
234#define CONFIG_SYS_NAND_BASE 0xE0600000
235#endif
236
Scott Woode8d3ca82010-08-30 18:04:52 -0500237#define CONFIG_MTD_DEVICE
238#define CONFIG_MTD_PARTITION
239#define CONFIG_CMD_MTDPARTS
240#define MTDIDS_DEFAULT "nand0=e0600000.flash"
Joe Hershberger6f681b72011-10-11 23:57:11 -0500241#define MTDPARTS_DEFAULT \
Scott Woode8d3ca82010-08-30 18:04:52 -0500242 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dave Liu1ac57442008-11-04 14:55:06 +0800245#define CONFIG_MTD_NAND_VERIFY_WRITE 1
246#define CONFIG_CMD_NAND 1
247#define CONFIG_NAND_FSL_ELBC 1
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500248#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
249#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800250
Anton Vorontsov2e950042009-11-24 20:12:12 +0300251#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
252#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
253#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
254#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
255#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
256
257#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500258 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500259 | BR_PS_8 /* 8 bit port */ \
Dave Liu8bd522c2008-01-11 18:48:24 +0800260 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500261 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500262#define CONFIG_SYS_NAND_OR_PRELIM \
263 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800264 | OR_FCM_CSCT \
265 | OR_FCM_CST \
266 | OR_FCM_CHT \
267 | OR_FCM_SCY_1 \
268 | OR_FCM_TRLX \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500269 | OR_FCM_EHTR)
Dave Liu8bd522c2008-01-11 18:48:24 +0800270 /* 0xFFFF8396 */
271
Anton Vorontsov2e950042009-11-24 20:12:12 +0300272#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
273#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
274#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
275#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Anton Vorontsov2e950042009-11-24 20:12:12 +0300276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500278#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu8bd522c2008-01-11 18:48:24 +0800279
Anton Vorontsov2e950042009-11-24 20:12:12 +0300280#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
281#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
282
283#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
284 !defined(CONFIG_NAND_SPL)
285#define CONFIG_SYS_RAMBOOT
286#else
287#undef CONFIG_SYS_RAMBOOT
288#endif
289
Dave Liu8bd522c2008-01-11 18:48:24 +0800290/*
291 * Serial Port
292 */
293#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_NS16550
295#define CONFIG_SYS_NS16550_SERIAL
296#define CONFIG_SYS_NS16550_REG_SIZE 1
Anton Vorontsov2e950042009-11-24 20:12:12 +0300297#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Dave Liu8bd522c2008-01-11 18:48:24 +0800298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu8bd522c2008-01-11 18:48:24 +0800301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
303#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu8bd522c2008-01-11 18:48:24 +0800304
305/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_HUSH_PARSER
Dave Liu8bd522c2008-01-11 18:48:24 +0800307
308/* Pass open firmware flat tree */
309#define CONFIG_OF_LIBFDT 1
310#define CONFIG_OF_BOARD_SETUP 1
311#define CONFIG_OF_STDOUT_VIA_ALIAS 1
312
313/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200314#define CONFIG_SYS_I2C
315#define CONFIG_SYS_I2C_FSL
316#define CONFIG_SYS_FSL_I2C_SPEED 400000
317#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
318#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
319#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu8bd522c2008-01-11 18:48:24 +0800320
321/*
322 * Board info - revision and where boot from
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
Dave Liu8bd522c2008-01-11 18:48:24 +0800325
326/*
327 * Config on-board RTC
328 */
329#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800331
332/*
333 * General PCI
334 * Addresses are mapped 1-1.
335 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500336#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
337#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
338#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
340#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
341#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
342#define CONFIG_SYS_PCI_IO_BASE 0x00000000
343#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
344#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu8bd522c2008-01-11 18:48:24 +0800345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
347#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
348#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800349
Anton Vorontsov8f11e342009-01-08 04:26:17 +0300350#define CONFIG_SYS_PCIE1_BASE 0xA0000000
351#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
352#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
353#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
354#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
355#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
356#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
357#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
358#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
359
360#define CONFIG_SYS_PCIE2_BASE 0xC0000000
361#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
362#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
363#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
364#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
365#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
366#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
367#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
368#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
369
Dave Liu8bd522c2008-01-11 18:48:24 +0800370#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000371#define CONFIG_PCI_INDIRECT_BRIDGE
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500372#define CONFIG_PCIE
Dave Liu8bd522c2008-01-11 18:48:24 +0800373
Dave Liu8bd522c2008-01-11 18:48:24 +0800374#define CONFIG_PCI_PNP /* do pci plug-and-play */
375
376#define CONFIG_EEPRO100
377#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu8bd522c2008-01-11 18:48:24 +0800379
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400380#define CONFIG_HAS_FSL_DR_USB
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530381#define CONFIG_SYS_SCCR_USBDRCM 3
382
383#define CONFIG_CMD_USB
384#define CONFIG_USB_STORAGE
385#define CONFIG_USB_EHCI
386#define CONFIG_USB_EHCI_FSL
Joe Hershberger6f681b72011-10-11 23:57:11 -0500387#define CONFIG_USB_PHY_TYPE "utmi"
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530388#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400389
Dave Liu8bd522c2008-01-11 18:48:24 +0800390/*
391 * TSEC
392 */
393#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500395#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500397#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu8bd522c2008-01-11 18:48:24 +0800398
399/*
400 * TSEC ethernet configuration
401 */
402#define CONFIG_MII 1 /* MII PHY management */
403#define CONFIG_TSEC1 1
404#define CONFIG_TSEC1_NAME "eTSEC0"
405#define CONFIG_TSEC2 1
406#define CONFIG_TSEC2_NAME "eTSEC1"
407#define TSEC1_PHY_ADDR 0
408#define TSEC2_PHY_ADDR 1
409#define TSEC1_PHYIDX 0
410#define TSEC2_PHYIDX 0
411#define TSEC1_FLAGS TSEC_GIGABIT
412#define TSEC2_FLAGS TSEC_GIGABIT
413
414/* Options are: eTSEC[0-1] */
415#define CONFIG_ETHPRIME "eTSEC1"
416
417/*
Kim Phillips730e7922008-03-28 14:31:23 -0500418 * SATA
419 */
420#define CONFIG_LIBATA
421#define CONFIG_FSL_SATA
422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500424#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500426#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
427#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500428#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500430#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
431#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500432
433#ifdef CONFIG_FSL_SATA
434#define CONFIG_LBA48
435#define CONFIG_CMD_SATA
436#define CONFIG_DOS_PARTITION
437#define CONFIG_CMD_EXT2
438#endif
439
440/*
Dave Liu8bd522c2008-01-11 18:48:24 +0800441 * Environment
442 */
Masahiro Yamadad0fb0fc2014-06-04 10:26:51 +0900443#if !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200444 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger6f681b72011-10-11 23:57:11 -0500445 #define CONFIG_ENV_ADDR \
446 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200447 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
448 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800449#else
Joe Hershberger6f681b72011-10-11 23:57:11 -0500450 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200451 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200453 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800454#endif
455
456#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu8bd522c2008-01-11 18:48:24 +0800458
459/*
460 * BOOTP options
461 */
462#define CONFIG_BOOTP_BOOTFILESIZE
463#define CONFIG_BOOTP_BOOTPATH
464#define CONFIG_BOOTP_GATEWAY
465#define CONFIG_BOOTP_HOSTNAME
466
467/*
468 * Command line configuration.
469 */
470#include <config_cmd_default.h>
471
472#define CONFIG_CMD_PING
473#define CONFIG_CMD_I2C
474#define CONFIG_CMD_MII
475#define CONFIG_CMD_DATE
476#define CONFIG_CMD_PCI
477
Masahiro Yamadad0fb0fc2014-06-04 10:26:51 +0900478#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500479 #undef CONFIG_CMD_SAVEENV
Dave Liu8bd522c2008-01-11 18:48:24 +0800480 #undef CONFIG_CMD_LOADS
481#endif
482
483#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500484#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu8bd522c2008-01-11 18:48:24 +0800485
486#undef CONFIG_WATCHDOG /* watchdog disabled */
487
488/*
489 * Miscellaneous configurable options
490 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_LONGHELP /* undef to save memory */
492#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu8bd522c2008-01-11 18:48:24 +0800493
494#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800496#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800498#endif
499
Joe Hershberger6f681b72011-10-11 23:57:11 -0500500 /* Print Buffer Size */
501#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
502#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
503 /* Boot Argument Buffer Size */
504#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu8bd522c2008-01-11 18:48:24 +0800505
506/*
507 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700508 * have to be in the first 256 MB of memory, since this is
Dave Liu8bd522c2008-01-11 18:48:24 +0800509 * the maximum mapped by the Linux kernel during initialization.
510 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500511#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu8bd522c2008-01-11 18:48:24 +0800512
513/*
514 * Core HID Setup
515 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500516#define CONFIG_SYS_HID0_INIT 0x000000000
517#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
518 HID0_ENABLE_INSTRUCTION_CACHE | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800519 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu8bd522c2008-01-11 18:48:24 +0800521
522/*
523 * MMU Setup
524 */
Becky Bruce31d82672008-05-08 19:02:12 -0500525#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu8bd522c2008-01-11 18:48:24 +0800526
527/* DDR: cache cacheable */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500528#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500529 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500530 | BATL_MEMCOHERENCE)
531#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
532 | BATU_BL_128M \
533 | BATU_VS \
534 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
536#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu8bd522c2008-01-11 18:48:24 +0800537
538/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500539#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500540 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500541 | BATL_CACHEINHIBIT \
542 | BATL_GUARDEDSTORAGE)
543#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
544 | BATU_BL_8M \
545 | BATU_VS \
546 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
548#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu8bd522c2008-01-11 18:48:24 +0800549
550/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500551#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500552 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500553 | BATL_MEMCOHERENCE)
554#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
555 | BATU_BL_32M \
556 | BATU_VS \
557 | BATU_VP)
558#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500559 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500560 | BATL_CACHEINHIBIT \
561 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu8bd522c2008-01-11 18:48:24 +0800563
564/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500565#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger6f681b72011-10-11 23:57:11 -0500566#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
567 | BATU_BL_128K \
568 | BATU_VS \
569 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
571#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu8bd522c2008-01-11 18:48:24 +0800572
573/* PCI MEM space: cacheable */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500574#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500575 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500576 | BATL_MEMCOHERENCE)
577#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
578 | BATU_BL_256M \
579 | BATU_VS \
580 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
582#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu8bd522c2008-01-11 18:48:24 +0800583
584/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500585#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500586 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500587 | BATL_CACHEINHIBIT \
588 | BATL_GUARDEDSTORAGE)
589#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
590 | BATU_BL_256M \
591 | BATU_VS \
592 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200593#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
594#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu8bd522c2008-01-11 18:48:24 +0800595
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_IBAT6L 0
597#define CONFIG_SYS_IBAT6U 0
598#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
599#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu8bd522c2008-01-11 18:48:24 +0800600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200601#define CONFIG_SYS_IBAT7L 0
602#define CONFIG_SYS_IBAT7U 0
603#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
604#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu8bd522c2008-01-11 18:48:24 +0800605
Dave Liu8bd522c2008-01-11 18:48:24 +0800606#if defined(CONFIG_CMD_KGDB)
607#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu8bd522c2008-01-11 18:48:24 +0800608#endif
609
610/*
611 * Environment Configuration
612 */
613
614#define CONFIG_ENV_OVERWRITE
615
616#if defined(CONFIG_TSEC_ENET)
617#define CONFIG_HAS_ETH0
Dave Liu8bd522c2008-01-11 18:48:24 +0800618#define CONFIG_HAS_ETH1
Dave Liu8bd522c2008-01-11 18:48:24 +0800619#endif
620
621#define CONFIG_BAUDRATE 115200
622
Kim Phillips79f516b2009-08-21 16:34:38 -0500623#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu8bd522c2008-01-11 18:48:24 +0800624
625#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
626#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
627
628#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500629 "netdev=eth0\0" \
630 "consoledev=ttyS0\0" \
631 "ramdiskaddr=1000000\0" \
632 "ramdiskfile=ramfs.83xx\0" \
633 "fdtaddr=780000\0" \
634 "fdtfile=mpc8315erdb.dtb\0" \
635 "usb_phy_type=utmi\0" \
636 ""
Dave Liu8bd522c2008-01-11 18:48:24 +0800637
638#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500639 "setenv bootargs root=/dev/nfs rw " \
640 "nfsroot=$serverip:$rootpath " \
641 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
642 "$netdev:off " \
643 "console=$consoledev,$baudrate $othbootargs;" \
644 "tftp $loadaddr $bootfile;" \
645 "tftp $fdtaddr $fdtfile;" \
646 "bootm $loadaddr - $fdtaddr"
Dave Liu8bd522c2008-01-11 18:48:24 +0800647
648#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500649 "setenv bootargs root=/dev/ram rw " \
650 "console=$consoledev,$baudrate $othbootargs;" \
651 "tftp $ramdiskaddr $ramdiskfile;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu8bd522c2008-01-11 18:48:24 +0800655
656
657#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
658
659#endif /* __CONFIG_H */