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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +09002/*
3 * Configuation settings for the Hitachi Solution Engine 7750
4 *
5 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +09006 */
7
8#ifndef __MS7750SE_H
9#define __MS7750SE_H
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090010
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090011#define CONFIG_CPU_SH7750 1
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090012/* #define CONFIG_CPU_SH7751 1 */
13/* #define CONFIG_CPU_TYPE_R 1 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090014#define __LITTLE_ENDIAN__ 1
15
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020016#define CONFIG_DISPLAY_BOARDINFO
17
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090018/*
19 * Command line configuration.
20 */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090021#define CONFIG_CONS_SCIF1 1
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090022
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090023#define CONFIG_ENV_OVERWRITE 1
24
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090025/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
27#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090028
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090030
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +020032#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090033
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090034/* NOR Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
36#define CONFIG_SYS_FLASH_BASE (0xA0000000)
37#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
Wolfgang Denk53677ef2008-05-20 16:00:29 +020038 * Flash memory banks
39 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_MAX_FLASH_SECT 142
41#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090042
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
44#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
45#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
46#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090047
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
49#define CONFIG_SYS_RX_ETH_BUFFER (8)
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020052#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
54#undef CONFIG_SYS_FLASH_QUIET_TEST
55#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090056
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020057#define CONFIG_ENV_SECT_SIZE 0x20000
58#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
60#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
61#define CONFIG_SYS_FLASH_WRITE_TOUT 500
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090062
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090063/* Board Clock */
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090064#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090065#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
66#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020067#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu69df3c42007-05-13 21:01:03 +090068
Nobuhiro Iwamatsu047375b2007-09-23 02:19:24 +090069#endif /* __MS7750SE_H */