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Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -04001/*
2 * Ethernet driver for TI K2HK EVM.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#include <common.h>
10#include <command.h>
11
12#include <net.h>
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +030013#include <phy.h>
Khoronzhuk, Ivanc05d05e2014-10-17 21:01:15 +030014#include <errno.h>
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040015#include <miiphy.h>
16#include <malloc.h>
Khoronzhuk, Ivanef454712014-09-05 19:02:47 +030017#include <asm/ti-common/keystone_nav.h>
Khoronzhuk, Ivan0935cac2014-09-29 22:17:22 +030018#include <asm/ti-common/keystone_net.h>
Khoronzhuk, Ivana43febd2014-10-22 17:18:21 +030019#include <asm/ti-common/keystone_serdes.h>
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040020
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040021unsigned int emac_open;
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030022static struct mii_dev *mdio_bus;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040023static unsigned int sys_has_mdio = 1;
24
25#ifdef KEYSTONE2_EMAC_GIG_ENABLE
26#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
27#else
28#define emac_gigabit_enable(x) /* no gigabit to enable */
29#endif
30
31#define RX_BUFF_NUMS 24
32#define RX_BUFF_LEN 1520
33#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
Khoronzhuk, Ivanc05d05e2014-10-17 21:01:15 +030034#define SGMII_ANEG_TIMEOUT 4000
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040035
36static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
37
38struct rx_buff_desc net_rx_buffs = {
39 .buff_ptr = rx_buffs,
40 .num_buffs = RX_BUFF_NUMS,
41 .buff_len = RX_BUFF_LEN,
42 .rx_flow = 22,
43};
44
Khoronzhuk, Ivana43febd2014-10-22 17:18:21 +030045static void keystone2_net_serdes_setup(void);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040046
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040047int keystone2_eth_read_mac_addr(struct eth_device *dev)
48{
49 struct eth_priv_t *eth_priv;
50 u32 maca = 0;
51 u32 macb = 0;
52
53 eth_priv = (struct eth_priv_t *)dev->priv;
54
55 /* Read the e-fuse mac address */
56 if (eth_priv->slave_port == 1) {
57 maca = __raw_readl(MAC_ID_BASE_ADDR);
58 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
59 }
60
61 dev->enetaddr[0] = (macb >> 8) & 0xff;
62 dev->enetaddr[1] = (macb >> 0) & 0xff;
63 dev->enetaddr[2] = (maca >> 24) & 0xff;
64 dev->enetaddr[3] = (maca >> 16) & 0xff;
65 dev->enetaddr[4] = (maca >> 8) & 0xff;
66 dev->enetaddr[5] = (maca >> 0) & 0xff;
67
68 return 0;
69}
70
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030071/* MDIO */
72
73static int keystone2_mdio_reset(struct mii_dev *bus)
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040074{
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030075 u_int32_t clkdiv;
76 struct mdio_regs *adap_mdio = bus->priv;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040077
78 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
79
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030080 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
81 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040082 &adap_mdio->control);
83
84 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
85 ;
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030086
87 return 0;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040088}
89
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030090/**
91 * keystone2_mdio_read - read a PHY register via MDIO interface.
92 * Blocks until operation is complete.
93 */
94static int keystone2_mdio_read(struct mii_dev *bus,
95 int addr, int devad, int reg)
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040096{
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +030097 int tmp;
98 struct mdio_regs *adap_mdio = bus->priv;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -040099
100 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
101 ;
102
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300103 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
104 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400105 &adap_mdio->useraccess0);
106
107 /* Wait for command to complete */
108 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
109 ;
110
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300111 if (tmp & MDIO_USERACCESS0_ACK)
112 return tmp & 0xffff;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400113
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400114 return -1;
115}
116
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300117/**
118 * keystone2_mdio_write - write to a PHY register via MDIO interface.
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400119 * Blocks until operation is complete.
120 */
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300121static int keystone2_mdio_write(struct mii_dev *bus,
122 int addr, int devad, int reg, u16 val)
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400123{
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300124 struct mdio_regs *adap_mdio = bus->priv;
125
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400126 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
127 ;
128
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300129 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
130 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
131 (val & 0xffff), &adap_mdio->useraccess0);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400132
133 /* Wait for command to complete */
134 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
135 ;
136
137 return 0;
138}
139
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400140static void __attribute__((unused))
141 keystone2_eth_gigabit_enable(struct eth_device *dev)
142{
143 u_int16_t data;
144 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
145
146 if (sys_has_mdio) {
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300147 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
148 MDIO_DEVAD_NONE, 0);
149 /* speed selection MSB */
150 if (!(data & (1 << 6)))
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400151 return;
152 }
153
154 /*
155 * Check if link detected is giga-bit
156 * If Gigabit mode detected, enable gigbit in MAC
157 */
Hao Zhangb2cfe322014-09-29 22:17:20 +0300158 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
159 CPGMACSL_REG_CTL) |
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400160 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
Hao Zhangb2cfe322014-09-29 22:17:20 +0300161 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400162}
163
164int keystone_sgmii_link_status(int port)
165{
166 u32 status = 0;
167
168 status = __raw_readl(SGMII_STATUS_REG(port));
169
Khoronzhuk, Ivana4d2ade2014-10-17 20:44:36 +0300170 return (status & SGMII_REG_STATUS_LOCK) &&
171 (status & SGMII_REG_STATUS_LINK);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400172}
173
Khoronzhuk, Ivanc05d05e2014-10-17 21:01:15 +0300174int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400175{
176 unsigned int i, status, mask;
177 unsigned int mr_adv_ability, control;
178
179 switch (interface) {
180 case SGMII_LINK_MAC_MAC_AUTONEG:
181 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
182 SGMII_REG_MR_ADV_LINK |
183 SGMII_REG_MR_ADV_FULL_DUPLEX |
184 SGMII_REG_MR_ADV_GIG_MODE);
185 control = (SGMII_REG_CONTROL_MASTER |
186 SGMII_REG_CONTROL_AUTONEG);
187
188 break;
189 case SGMII_LINK_MAC_PHY:
190 case SGMII_LINK_MAC_PHY_FORCED:
191 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
192 control = SGMII_REG_CONTROL_AUTONEG;
193
194 break;
195 case SGMII_LINK_MAC_MAC_FORCED:
196 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
197 SGMII_REG_MR_ADV_LINK |
198 SGMII_REG_MR_ADV_FULL_DUPLEX |
199 SGMII_REG_MR_ADV_GIG_MODE);
200 control = SGMII_REG_CONTROL_MASTER;
201
202 break;
203 case SGMII_LINK_MAC_FIBER:
204 mr_adv_ability = 0x20;
205 control = SGMII_REG_CONTROL_AUTONEG;
206
207 break;
208 default:
209 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
210 control = SGMII_REG_CONTROL_AUTONEG;
211 }
212
213 __raw_writel(0, SGMII_CTL_REG(port));
214
215 /*
216 * Wait for the SerDes pll to lock,
217 * but don't trap if lock is never read
218 */
219 for (i = 0; i < 1000; i++) {
220 udelay(2000);
221 status = __raw_readl(SGMII_STATUS_REG(port));
222 if ((status & SGMII_REG_STATUS_LOCK) != 0)
223 break;
224 }
225
226 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
227 __raw_writel(control, SGMII_CTL_REG(port));
228
229
230 mask = SGMII_REG_STATUS_LINK;
231
232 if (control & SGMII_REG_CONTROL_AUTONEG)
233 mask |= SGMII_REG_STATUS_AUTONEG;
234
Khoronzhuk, Ivanc05d05e2014-10-17 21:01:15 +0300235 status = __raw_readl(SGMII_STATUS_REG(port));
236 if ((status & mask) == mask)
237 return 0;
238
239 printf("\n%s Waiting for SGMII auto negotiation to complete",
240 phy_dev->dev->name);
241 while ((status & mask) != mask) {
242 /*
243 * Timeout reached ?
244 */
245 if (i > SGMII_ANEG_TIMEOUT) {
246 puts(" TIMEOUT !\n");
247 phy_dev->link = 0;
248 return 0;
249 }
250
251 if (ctrlc()) {
252 puts("user interrupt!\n");
253 phy_dev->link = 0;
254 return -EINTR;
255 }
256
257 if ((i++ % 500) == 0)
258 printf(".");
259
260 udelay(1000); /* 1 ms */
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400261 status = __raw_readl(SGMII_STATUS_REG(port));
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400262 }
Khoronzhuk, Ivanc05d05e2014-10-17 21:01:15 +0300263 puts(" done\n");
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400264
265 return 0;
266}
267
268int mac_sl_reset(u32 port)
269{
270 u32 i, v;
271
272 if (port >= DEVICE_N_GMACSL_PORTS)
273 return GMACSL_RET_INVALID_PORT;
274
275 /* Set the soft reset bit */
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300276 writel(CPGMAC_REG_RESET_VAL_RESET,
277 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400278
279 /* Wait for the bit to clear */
280 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300281 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400282 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
283 CPGMAC_REG_RESET_VAL_RESET)
284 return GMACSL_RET_OK;
285 }
286
287 /* Timeout on the reset */
288 return GMACSL_RET_WARN_RESET_INCOMPLETE;
289}
290
291int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
292{
293 u32 v, i;
294 int ret = GMACSL_RET_OK;
295
296 if (port >= DEVICE_N_GMACSL_PORTS)
297 return GMACSL_RET_INVALID_PORT;
298
299 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
300 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
301 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
302 }
303
304 /* Must wait if the device is undergoing reset */
305 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300306 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400307 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
308 CPGMAC_REG_RESET_VAL_RESET)
309 break;
310 }
311
312 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
313 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
314
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300315 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
316 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400317
Khoronzhuk, Ivan6c0fb412014-10-29 13:09:33 +0200318#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
Khoronzhuk, Ivanff11c762014-10-17 21:01:14 +0300319 /* Map RX packet flow priority to 0 */
320 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
321#endif
322
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400323 return ret;
324}
325
326int ethss_config(u32 ctl, u32 max_pkt_size)
327{
328 u32 i;
329
330 /* Max length register */
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300331 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400332
333 /* Control register */
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300334 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400335
336 /* All statistics enabled by default */
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300337 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
338 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400339
340 /* Reset and enable the ALE */
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300341 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
342 CPSW_REG_VAL_ALE_CTL_BYPASS,
343 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400344
345 /* All ports put into forward mode */
346 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
Khoronzhuk, Ivane6c94282014-08-28 16:07:45 +0300347 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
348 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400349
350 return 0;
351}
352
353int ethss_start(void)
354{
355 int i;
356 struct mac_sl_cfg cfg;
357
358 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
359 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
360
361 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
362 mac_sl_reset(i);
363 mac_sl_config(i, &cfg);
364 }
365
366 return 0;
367}
368
369int ethss_stop(void)
370{
371 int i;
372
373 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
374 mac_sl_reset(i);
375
376 return 0;
377}
378
379int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
380{
381 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
382 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
383
Khoronzhuk, Ivan9ea90212014-09-05 19:02:48 +0300384 return ksnav_send(&netcp_pktdma, buffer,
385 num_bytes, (slave_port_num) << 16);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400386}
387
388/* Eth device open */
389static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
390{
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400391 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +0300392 struct phy_device *phy_dev = eth_priv->phy_dev;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400393
394 debug("+ emac_open\n");
395
396 net_rx_buffs.rx_flow = eth_priv->rx_flow;
397
398 sys_has_mdio =
399 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
400
Khoronzhuk, Ivan6c0fb412014-10-29 13:09:33 +0200401 if (sys_has_mdio)
402 keystone2_mdio_reset(mdio_bus);
403
Khoronzhuk, Ivanc05d05e2014-10-17 21:01:15 +0300404 keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400405 eth_priv->sgmii_link_type);
406
407 udelay(10000);
408
409 /* On chip switch configuration */
410 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
411
412 /* TODO: add error handling code */
413 if (qm_init()) {
414 printf("ERROR: qm_init()\n");
415 return -1;
416 }
Khoronzhuk, Ivan9ea90212014-09-05 19:02:48 +0300417 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400418 qm_close();
419 printf("ERROR: netcp_init()\n");
420 return -1;
421 }
422
423 /*
424 * Streaming switch configuration. If not present this
425 * statement is defined to void in target.h.
426 * If present this is usually defined to a series of register writes
427 */
428 hw_config_streaming_switch();
429
430 if (sys_has_mdio) {
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300431 keystone2_mdio_reset(mdio_bus);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400432
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +0300433 phy_startup(phy_dev);
434 if (phy_dev->link == 0) {
Khoronzhuk, Ivan9ea90212014-09-05 19:02:48 +0300435 ksnav_close(&netcp_pktdma);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400436 qm_close();
437 return -1;
438 }
439 }
440
441 emac_gigabit_enable(dev);
442
443 ethss_start();
444
445 debug("- emac_open\n");
446
447 emac_open = 1;
448
449 return 0;
450}
451
452/* Eth device close */
453void keystone2_eth_close(struct eth_device *dev)
454{
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +0300455 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
456 struct phy_device *phy_dev = eth_priv->phy_dev;
457
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400458 debug("+ emac_close\n");
459
460 if (!emac_open)
461 return;
462
463 ethss_stop();
464
Khoronzhuk, Ivan9ea90212014-09-05 19:02:48 +0300465 ksnav_close(&netcp_pktdma);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400466 qm_close();
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +0300467 phy_shutdown(phy_dev);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400468
469 emac_open = 0;
470
471 debug("- emac_close\n");
472}
473
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400474/*
475 * This function sends a single packet on the network and returns
476 * positive number (number of bytes transmitted) or negative for error
477 */
478static int keystone2_eth_send_packet(struct eth_device *dev,
479 void *packet, int length)
480{
481 int ret_status = -1;
482 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
Khoronzhuk, Ivana4d2ade2014-10-17 20:44:36 +0300483 struct phy_device *phy_dev = eth_priv->phy_dev;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400484
Khoronzhuk, Ivana4d2ade2014-10-17 20:44:36 +0300485 genphy_update_link(phy_dev);
486 if (phy_dev->link == 0)
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400487 return -1;
488
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400489 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
490 return ret_status;
491
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400492 return length;
493}
494
495/*
496 * This function handles receipt of a packet from the network
497 */
498static int keystone2_eth_rcv_packet(struct eth_device *dev)
499{
500 void *hd;
501 int pkt_size;
502 u32 *pkt;
503
Khoronzhuk, Ivan9ea90212014-09-05 19:02:48 +0300504 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400505 if (hd == NULL)
506 return 0;
507
508 NetReceive((uchar *)pkt, pkt_size);
509
Khoronzhuk, Ivan9ea90212014-09-05 19:02:48 +0300510 ksnav_release_rxhd(&netcp_pktdma, hd);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400511
512 return pkt_size;
513}
514
515/*
516 * This function initializes the EMAC hardware.
517 */
518int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
519{
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300520 int res;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400521 struct eth_device *dev;
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +0300522 struct phy_device *phy_dev;
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400523
524 dev = malloc(sizeof(struct eth_device));
525 if (dev == NULL)
526 return -1;
527
528 memset(dev, 0, sizeof(struct eth_device));
529
530 strcpy(dev->name, eth_priv->int_name);
531 dev->priv = eth_priv;
532
533 keystone2_eth_read_mac_addr(dev);
534
535 dev->iobase = 0;
536 dev->init = keystone2_eth_open;
537 dev->halt = keystone2_eth_close;
538 dev->send = keystone2_eth_send_packet;
539 dev->recv = keystone2_eth_rcv_packet;
540
541 eth_register(dev);
542
Khoronzhuk, Ivan550c5ce2014-10-17 20:44:34 +0300543 /* Register MDIO bus if it's not registered yet */
544 if (!mdio_bus) {
545 mdio_bus = mdio_alloc();
546 mdio_bus->read = keystone2_mdio_read;
547 mdio_bus->write = keystone2_mdio_write;
548 mdio_bus->reset = keystone2_mdio_reset;
549 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
550 sprintf(mdio_bus->name, "ethernet-mdio");
551
552 res = mdio_register(mdio_bus);
553 if (res)
554 return res;
555 }
556
Vitaly Andrianov312aca42015-02-11 14:05:41 -0500557 keystone2_net_serdes_setup();
558
Khoronzhuk, Ivan3fe93622014-10-17 20:44:35 +0300559 /* Create phy device and bind it with driver */
560#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
561 phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
562 dev, PHY_INTERFACE_MODE_SGMII);
563 phy_config(phy_dev);
564#else
565 phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
566 PHY_INTERFACE_MODE_SGMII);
567 phy_dev->dev = dev;
568#endif
569 eth_priv->phy_dev = phy_dev;
570
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400571 return 0;
572}
573
Hao Zhang92a16c82014-10-22 17:18:23 +0300574struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
575 .clk = SERDES_CLOCK_156P25M,
576 .rate = SERDES_RATE_5G,
577 .rate_mode = SERDES_QUARTER_RATE,
578 .intf = SERDES_PHY_SGMII,
579 .loopback = 0,
580};
581
Khoronzhuk, Ivana43febd2014-10-22 17:18:21 +0300582static void keystone2_net_serdes_setup(void)
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400583{
Hao Zhang92a16c82014-10-22 17:18:23 +0300584 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
585 &ks2_serdes_sgmii_156p25mhz,
586 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
587
Khoronzhuk, Ivan87ac27b2014-10-29 13:09:32 +0200588#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
Khoronzhuk, Ivan3c615022014-10-17 21:01:13 +0300589 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
590 &ks2_serdes_sgmii_156p25mhz,
591 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
592#endif
593
Hao Zhang92a16c82014-10-22 17:18:23 +0300594 /* wait till setup */
595 udelay(5000);
Karicheri, Muralidharanfc9a8e82014-04-01 15:01:13 -0400596}