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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Graeme Russabf0cd32009-02-24 21:13:40 +11002/*
3 * (C) Copyright 2009
Graeme Russdbf71152011-04-13 19:43:26 +10004 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russabf0cd32009-02-24 21:13:40 +11005 *
6 * (C) Copyright 2007
Graeme Russdbf71152011-04-13 19:43:26 +10007 * Daniel Hellstrom, Gaisler Research, <daniel@gaisler.com>
Graeme Russabf0cd32009-02-24 21:13:40 +11008 *
9 * (C) Copyright 2006
Graeme Russdbf71152011-04-13 19:43:26 +100010 * Detlev Zundel, DENX Software Engineering, <dzu@denx.de>
Graeme Russabf0cd32009-02-24 21:13:40 +110011 *
12 * (C) Copyright -2003
Graeme Russdbf71152011-04-13 19:43:26 +100013 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
Graeme Russabf0cd32009-02-24 21:13:40 +110014 *
15 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +020016 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
Graeme Russabf0cd32009-02-24 21:13:40 +110017 *
18 * (C) Copyright 2001
Graeme Russdbf71152011-04-13 19:43:26 +100019 * Josh Huber, Mission Critical Linux, Inc, <huber@mclx.com>
Graeme Russabf0cd32009-02-24 21:13:40 +110020 */
21
22/*
23 * This file contains the high-level API for the interrupt sub-system
Graeme Russdbf71152011-04-13 19:43:26 +100024 * of the x86 port of U-Boot. Most of the functionality has been
Graeme Russabf0cd32009-02-24 21:13:40 +110025 * shamelessly stolen from the leon2 / leon3 ports of U-Boot.
26 * Daniel Hellstrom, Detlev Zundel, Wolfgang Denk and Josh Huber are
27 * credited for the corresponding work on those ports. The original
Graeme Russdbf71152011-04-13 19:43:26 +100028 * interrupt handling routines for the x86 port were written by
Albert ARIBAUDfa82f872011-08-04 18:45:45 +020029 * Daniel Engström
Graeme Russabf0cd32009-02-24 21:13:40 +110030 */
31
32#include <common.h>
33#include <asm/interrupt.h>
34
Simon Glassc2bf0df2017-01-16 07:04:14 -070035#if !CONFIG_IS_ENABLED(X86_64)
36
Graeme Russabf0cd32009-02-24 21:13:40 +110037struct irq_action {
38 interrupt_handler_t *handler;
39 void *arg;
40 unsigned int count;
41};
42
Bin Meng6c505272015-10-22 19:13:26 -070043static struct irq_action irq_handlers[SYS_NUM_IRQS] = { {0} };
Graeme Russ83088af2011-11-08 02:33:15 +000044static int spurious_irq_cnt;
45static int spurious_irq;
Graeme Russabf0cd32009-02-24 21:13:40 +110046
47void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
48{
49 int status;
50
Bin Meng6c505272015-10-22 19:13:26 -070051 if (irq < 0 || irq >= SYS_NUM_IRQS) {
Graeme Russabf0cd32009-02-24 21:13:40 +110052 printf("irq_install_handler: bad irq number %d\n", irq);
53 return;
54 }
55
56 if (irq_handlers[irq].handler != NULL)
57 printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
Graeme Russ83088af2011-11-08 02:33:15 +000058 (ulong) handler,
59 (ulong) irq_handlers[irq].handler);
Graeme Russabf0cd32009-02-24 21:13:40 +110060
Graeme Russ83088af2011-11-08 02:33:15 +000061 status = disable_interrupts();
Graeme Russabf0cd32009-02-24 21:13:40 +110062
Graeme Russ1c409bc2009-11-24 20:04:21 +110063 irq_handlers[irq].handler = handler;
Graeme Russabf0cd32009-02-24 21:13:40 +110064 irq_handlers[irq].arg = arg;
65 irq_handlers[irq].count = 0;
66
Bin Mengc6410102018-11-29 19:57:21 -080067 if (CONFIG_IS_ENABLED(I8259_PIC))
68 unmask_irq(irq);
Graeme Russabf0cd32009-02-24 21:13:40 +110069
70 if (status)
71 enable_interrupts();
72
73 return;
74}
75
76void irq_free_handler(int irq)
77{
78 int status;
79
Bin Meng6c505272015-10-22 19:13:26 -070080 if (irq < 0 || irq >= SYS_NUM_IRQS) {
Graeme Russabf0cd32009-02-24 21:13:40 +110081 printf("irq_free_handler: bad irq number %d\n", irq);
82 return;
83 }
84
Graeme Russ83088af2011-11-08 02:33:15 +000085 status = disable_interrupts();
Graeme Russabf0cd32009-02-24 21:13:40 +110086
Bin Mengc6410102018-11-29 19:57:21 -080087 if (CONFIG_IS_ENABLED(I8259_PIC))
88 mask_irq(irq);
Graeme Russabf0cd32009-02-24 21:13:40 +110089
90 irq_handlers[irq].handler = NULL;
91 irq_handlers[irq].arg = NULL;
92
93 if (status)
94 enable_interrupts();
95
96 return;
97}
98
Graeme Russ564a9982009-11-24 20:04:18 +110099void do_irq(int hw_irq)
Graeme Russabf0cd32009-02-24 21:13:40 +1100100{
Graeme Russ564a9982009-11-24 20:04:18 +1100101 int irq = hw_irq - 0x20;
102
Bin Meng6c505272015-10-22 19:13:26 -0700103 if (irq < 0 || irq >= SYS_NUM_IRQS) {
Graeme Russabf0cd32009-02-24 21:13:40 +1100104 printf("do_irq: bad irq number %d\n", irq);
105 return;
106 }
107
108 if (irq_handlers[irq].handler) {
Bin Mengc6410102018-11-29 19:57:21 -0800109 if (CONFIG_IS_ENABLED(I8259_PIC))
110 mask_irq(irq);
Graeme Russabf0cd32009-02-24 21:13:40 +1100111
112 irq_handlers[irq].handler(irq_handlers[irq].arg);
113 irq_handlers[irq].count++;
114
Bin Mengc6410102018-11-29 19:57:21 -0800115 if (CONFIG_IS_ENABLED(I8259_PIC)) {
116 unmask_irq(irq);
117 specific_eoi(irq);
118 }
Graeme Russabf0cd32009-02-24 21:13:40 +1100119 } else {
120 if ((irq & 7) != 7) {
121 spurious_irq_cnt++;
122 spurious_irq = irq;
123 }
124 }
125}
Simon Glassc2bf0df2017-01-16 07:04:14 -0700126#endif
Graeme Russabf0cd32009-02-24 21:13:40 +1100127
128#if defined(CONFIG_CMD_IRQ)
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200129int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Graeme Russabf0cd32009-02-24 21:13:40 +1100130{
Simon Glassc2bf0df2017-01-16 07:04:14 -0700131#if !CONFIG_IS_ENABLED(X86_64)
Graeme Russabf0cd32009-02-24 21:13:40 +1100132 int irq;
133
134 printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
Graeme Russ83088af2011-11-08 02:33:15 +0000135 spurious_irq_cnt, spurious_irq);
Graeme Russabf0cd32009-02-24 21:13:40 +1100136
Graeme Russ83088af2011-11-08 02:33:15 +0000137 printf("Interrupt-Information:\n");
138 printf("Nr Routine Arg Count\n");
Graeme Russabf0cd32009-02-24 21:13:40 +1100139
Bin Meng6c505272015-10-22 19:13:26 -0700140 for (irq = 0; irq < SYS_NUM_IRQS; irq++) {
Graeme Russabf0cd32009-02-24 21:13:40 +1100141 if (irq_handlers[irq].handler != NULL) {
Graeme Russ83088af2011-11-08 02:33:15 +0000142 printf("%02d %08lx %08lx %d\n",
Graeme Russabf0cd32009-02-24 21:13:40 +1100143 irq,
144 (ulong)irq_handlers[irq].handler,
145 (ulong)irq_handlers[irq].arg,
146 irq_handlers[irq].count);
147 }
148 }
Simon Glassc2bf0df2017-01-16 07:04:14 -0700149#endif
Graeme Russabf0cd32009-02-24 21:13:40 +1100150
151 return 0;
152}
153#endif