blob: 1f5a33d520bd159e9368ffccd196ed1b2373904e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tuomas Tynkkynen32f11822017-09-19 23:18:07 +03002/*
3 * Copyright (c) 2017 Tuomas Tynkkynen
Tuomas Tynkkynen32f11822017-09-19 23:18:07 +03004 */
5#include <common.h>
6#include <fdtdec.h>
7
Tuomas Tynkkynenddcca732018-01-11 16:11:23 +02008#ifdef CONFIG_ARM64
9#include <asm/armv8/mmu.h>
10
11static struct mm_region qemu_arm64_mem_map[] = {
12 {
13 /* Flash */
14 .virt = 0x00000000UL,
15 .phys = 0x00000000UL,
16 .size = 0x08000000UL,
17 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
18 PTE_BLOCK_INNER_SHARE
19 }, {
20 /* Peripherals */
21 .virt = 0x08000000UL,
22 .phys = 0x08000000UL,
23 .size = 0x38000000,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
25 PTE_BLOCK_NON_SHARE |
26 PTE_BLOCK_PXN | PTE_BLOCK_UXN
27 }, {
28 /* RAM */
29 .virt = 0x40000000UL,
30 .phys = 0x40000000UL,
Tuomas Tynkkynenf37770c2018-05-14 18:47:51 +030031 .size = 255UL * SZ_1G,
Tuomas Tynkkynenddcca732018-01-11 16:11:23 +020032 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
33 PTE_BLOCK_INNER_SHARE
34 }, {
35 /* List terminator */
36 0,
37 }
38};
39
40struct mm_region *mem_map = qemu_arm64_mem_map;
41#endif
42
Tuomas Tynkkynen32f11822017-09-19 23:18:07 +030043int board_init(void)
44{
45 return 0;
46}
47
48int dram_init(void)
49{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +053050 if (fdtdec_setup_mem_size_base() != 0)
Tuomas Tynkkynen32f11822017-09-19 23:18:07 +030051 return -EINVAL;
52
53 return 0;
54}
55
56int dram_init_banksize(void)
57{
58 fdtdec_setup_memory_banksize();
59
60 return 0;
61}
62
63void *board_fdt_blob_setup(void)
64{
65 /* QEMU loads a generated DTB for us at the start of RAM. */
66 return (void *)CONFIG_SYS_SDRAM_BASE;
67}