| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2007 Nobuhiro Iwamatsu |
| 4 | * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
| 5 | * |
| 6 | * u-boot/board/r7780mp/r7780mp.h |
| Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef _BOARD_R7780MP_R7780MP_H_ |
| 10 | #define _BOARD_R7780MP_R7780MP_H_ |
| 11 | |
| 12 | /* R7780MP's FPGA register map */ |
| 13 | #define FPGA_BASE 0xa4000000 |
| 14 | #define FPGA_IRLMSK (FPGA_BASE + 0x00) |
| 15 | #define FPGA_IRLMON (FPGA_BASE + 0x02) |
| 16 | #define FPGA_IRLPRI1 (FPGA_BASE + 0x04) |
| 17 | #define FPGA_IRLPRI2 (FPGA_BASE + 0x06) |
| 18 | #define FPGA_IRLPRI3 (FPGA_BASE + 0x08) |
| 19 | #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) |
| 20 | #define FPGA_RSTCTL (FPGA_BASE + 0x0C) |
| 21 | #define FPGA_PCIBD (FPGA_BASE + 0x0E) |
| 22 | #define FPGA_PCICD (FPGA_BASE + 0x10) |
| 23 | #define FPGA_EXTGIO (FPGA_BASE + 0x16) |
| 24 | #define FPGA_IVDRMON (FPGA_BASE + 0x18) |
| 25 | #define FPGA_IVDRCR (FPGA_BASE + 0x1A) |
| 26 | #define FPGA_OBLED (FPGA_BASE + 0x1C) |
| 27 | #define FPGA_OBSW (FPGA_BASE + 0x1E) |
| 28 | #define FPGA_TPCTL (FPGA_BASE + 0x100) |
| 29 | #define FPGA_TPDCKCTL (FPGA_BASE + 0x102) |
| 30 | #define FPGA_TPCLR (FPGA_BASE + 0x104) |
| 31 | #define FPGA_TPXPOS (FPGA_BASE + 0x106) |
| 32 | #define FPGA_TPYPOS (FPGA_BASE + 0x108) |
| 33 | #define FPGA_DBSW (FPGA_BASE + 0x200) |
| 34 | #define FPGA_VERSION (FPGA_BASE + 0x700) |
| 35 | #define FPGA_CFCTL (FPGA_BASE + 0x300) |
| 36 | #define FPGA_CFPOW (FPGA_BASE + 0x302) |
| 37 | #define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) |
| 38 | #define FPGA_PMR (FPGA_BASE + 0x900) |
| 39 | |
| 40 | #endif /* _BOARD_R7780RP_R7780RP_H_ */ |