blob: 35616557274bd0de7a3d2651a09d7774c6d965d8 [file] [log] [blame]
Heiko Schochere379c032014-07-18 06:07:22 +02001/*
2 * Copyright (C) 2013 Boundary Devices
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6/* ZQ Calibration */
7DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
8DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
9DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
10DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
11DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
12DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
13/*
14 * DQS gating, read delay, write delay calibration values
15 * based on calibration compare of 0x00ffff00
16 */
17DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
18DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
19DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
20DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
21DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
22DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
23DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
24DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
25/* read data bit delay */
26DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
27DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
28DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
29DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
30DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
31DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
32DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
33DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
34/* Complete calibration by forced measurment */
35DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
36DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
37/* in DDR3, 64-bit mode, only MMDC0 is initiated */
38DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
39DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
40DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
41DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
42DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
43DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
44DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
45DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
46DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
47DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
48DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
49/* MR2 */
50DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
51DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
52/* MR3 */
53DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
54DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
55/* MR1 */
56DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
57DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
58/* MR0 */
59DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
60DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
61/* ZQ calibration */
62DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
63DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
64/* final ddr setup */
65DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
66DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
67DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
68DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
69DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
70DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000