blob: 417b419d467cdfd2c426b0f0166044bcb60346f6 [file] [log] [blame]
Stephan Gerhold057b6132020-01-04 18:45:15 +01001// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2019 Stephan Gerhold <stephan@gerhold.net>
4 *
5 * Based on arch/arm/cpu/armv7/u8500/timer.c:
6 * Copyright (C) 2010 Linaro Limited
7 * John Rigby <john.rigby@linaro.org>
8 *
9 * Based on Linux kernel source and internal ST-Ericsson U-Boot source:
10 * Copyright (C) 2009 Alessandro Rubini
11 * Copyright (C) 2010 ST-Ericsson
12 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <timer.h>
18#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <linux/bitops.h>
Stephan Gerhold057b6132020-01-04 18:45:15 +010020
21#define MTU_NUM_TIMERS 4
22
23/* The timers */
24struct nomadik_mtu_timer_regs {
25 u32 lr; /* Load register */
26 u32 cv; /* Current value */
27 u32 cr; /* Control register */
28 u32 bglr; /* Background load register */
29};
30
31/* The MTU that contains the timers */
32struct nomadik_mtu_regs {
33 u32 imsc; /* Interrupt mask set/clear */
34 u32 ris; /* Raw interrupt status */
35 u32 mis; /* Masked interrupt status */
36 u32 icr; /* Interrupt clear register */
37
38 struct nomadik_mtu_timer_regs timers[MTU_NUM_TIMERS];
39};
40
41/* Bits for the control register */
42#define MTU_CR_ONESHOT BIT(0) /* if 0 = wraps reloading from BGLR */
43#define MTU_CR_32BITS BIT(1) /* if 0 = 16-bit counter */
44
45#define MTU_CR_PRESCALE_SHIFT 2
46#define MTU_CR_PRESCALE_1 (0 << MTU_CR_PRESCALE_SHIFT)
47#define MTU_CR_PRESCALE_16 (1 << MTU_CR_PRESCALE_SHIFT)
48#define MTU_CR_PRESCALE_256 (2 << MTU_CR_PRESCALE_SHIFT)
49
50#define MTU_CR_PERIODIC BIT(6) /* if 0 = free-running */
51#define MTU_CR_ENABLE BIT(7)
52
53struct nomadik_mtu_priv {
54 struct nomadik_mtu_timer_regs *timer;
55};
56
Sean Anderson8af7bb92020-10-07 14:37:44 -040057static u64 nomadik_mtu_get_count(struct udevice *dev)
Stephan Gerhold057b6132020-01-04 18:45:15 +010058{
59 struct nomadik_mtu_priv *priv = dev_get_priv(dev);
60
61 /* Decrementing counter: invert the value */
Sean Anderson8af7bb92020-10-07 14:37:44 -040062 return timer_conv_64(~readl(&priv->timer->cv));
Stephan Gerhold057b6132020-01-04 18:45:15 +010063}
64
65static int nomadik_mtu_probe(struct udevice *dev)
66{
67 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
68 struct nomadik_mtu_priv *priv = dev_get_priv(dev);
69 struct nomadik_mtu_regs *mtu;
70 fdt_addr_t addr;
71 u32 prescale;
72
73 addr = dev_read_addr(dev);
74 if (addr == FDT_ADDR_T_NONE)
75 return -EINVAL;
76
77 mtu = (struct nomadik_mtu_regs *)addr;
78 priv->timer = mtu->timers; /* Use first timer */
79
80 if (!uc_priv->clock_rate)
81 return -EINVAL;
82
83 /* Use divide-by-16 counter if tick rate is more than 32 MHz */
84 if (uc_priv->clock_rate > 32000000) {
85 uc_priv->clock_rate /= 16;
86 prescale = MTU_CR_PRESCALE_16;
87 } else {
88 prescale = MTU_CR_PRESCALE_1;
89 }
90
91 /* Configure a free-running, auto-wrap counter with selected prescale */
92 writel(MTU_CR_ENABLE | prescale | MTU_CR_32BITS, &priv->timer->cr);
93
94 return 0;
95}
96
97static const struct timer_ops nomadik_mtu_ops = {
98 .get_count = nomadik_mtu_get_count,
99};
100
101static const struct udevice_id nomadik_mtu_ids[] = {
102 { .compatible = "st,nomadik-mtu" },
103 {}
104};
105
106U_BOOT_DRIVER(nomadik_mtu) = {
107 .name = "nomadik_mtu",
108 .id = UCLASS_TIMER,
109 .of_match = nomadik_mtu_ids,
Simon Glass41575d82020-12-03 16:55:17 -0700110 .priv_auto = sizeof(struct nomadik_mtu_priv),
Stephan Gerhold057b6132020-01-04 18:45:15 +0100111 .probe = nomadik_mtu_probe,
112 .ops = &nomadik_mtu_ops,
113};