blob: 12cb0bc7805ac3af04fb6280b1ce33d91add8151 [file] [log] [blame]
Simon Glass6710b5b2012-02-27 10:52:39 +00001/dts-v1/;
2
3/memreserve/ 0x1c000000 0x04000000;
Tom Warren6c5be642013-02-21 12:31:27 +00004#include "tegra20.dtsi"
Simon Glass6710b5b2012-02-27 10:52:39 +00005
6/ {
7 model = "NVIDIA Seaboard";
8 compatible = "nvidia,seaboard", "nvidia,tegra20";
9
10 chosen {
11 bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
12 };
13
Simon Glass19201722012-02-27 10:52:46 +000014 aliases {
Tom Warren126685a2013-02-21 12:31:29 +000015 /* This defines the order of our ports */
Simon Glass19201722012-02-27 10:52:46 +000016 usb0 = "/usb@c5008000";
17 usb1 = "/usb@c5000000";
Simon Glass3682cc32012-02-29 07:31:27 +000018 i2c0 = "/i2c@7000d000";
19 i2c1 = "/i2c@7000c000";
20 i2c2 = "/i2c@7000c400";
21 i2c3 = "/i2c@7000c500";
Tom Warren126685a2013-02-21 12:31:29 +000022 sdhci0 = "/sdhci@c8000600";
23 sdhci1 = "/sdhci@c8000400";
Simon Glass19201722012-02-27 10:52:46 +000024 };
25
Simon Glass6710b5b2012-02-27 10:52:39 +000026 memory {
27 device_type = "memory";
28 reg = < 0x00000000 0x40000000 >;
29 };
30
Allen Martin36068ae2013-01-25 08:46:47 +000031 host1x {
32 status = "okay";
33 dc@54200000 {
34 status = "okay";
35 rgb {
36 status = "okay";
37 nvidia,panel = <&lcd_panel>;
38 };
39 };
40 };
41
Simon Glasscd474cb2012-02-28 08:07:49 +000042 /* This is not used in U-Boot, but is expected to be in kernel .dts */
43 i2c@7000d000 {
Simon Glass3682cc32012-02-29 07:31:27 +000044 clock-frequency = <100000>;
Simon Glasscd474cb2012-02-28 08:07:49 +000045 pmic@34 {
46 compatible = "ti,tps6586x";
47 reg = <0x34>;
48
49 clk_32k: clock {
50 compatible = "fixed-clock";
51 /*
52 * leave out for now due to CPP:
53 * #clock-cells = <0>;
54 */
55 clock-frequency = <32768>;
56 };
57 };
58 };
59
Simon Glass6710b5b2012-02-27 10:52:39 +000060 serial@70006300 {
61 clock-frequency = < 216000000 >;
62 };
63
Allen Martinb7723f32013-01-16 13:12:24 +000064 nand-controller@70008000 {
65 nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
66 nvidia,width = <8>;
67 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
68 nand@0 {
69 reg = <0>;
70 compatible = "hynix,hy27uf4g2b", "nand-flash";
71 };
Simon Glass6710b5b2012-02-27 10:52:39 +000072 };
Simon Glass3682cc32012-02-29 07:31:27 +000073
74 i2c@7000c000 {
75 clock-frequency = <100000>;
76 };
77
78 i2c@7000c400 {
79 status = "disabled";
80 };
81
82 i2c@7000c500 {
83 clock-frequency = <100000>;
84 };
Simon Glassd376e8d2012-04-05 11:55:15 +000085
Allen Martinb7723f32013-01-16 13:12:24 +000086 kbc@7000e200 {
87 linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
88 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
89 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
90 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
91 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
92 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
93 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
94 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
95 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
96 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
97 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
98 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
99 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
100 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
101 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
102 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
103 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
104 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
105 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
106 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
107 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
108 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
109 0x1f04008a>;
110 linux,fn-keymap = <0x05040002>;
111 };
112
Simon Glassd376e8d2012-04-05 11:55:15 +0000113 emc@7000f400 {
114 emc-table@190000 {
115 reg = < 190000 >;
116 compatible = "nvidia,tegra20-emc-table";
117 clock-frequency = < 190000 >;
118 nvidia,emc-registers = < 0x0000000c 0x00000026
119 0x00000009 0x00000003 0x00000004 0x00000004
120 0x00000002 0x0000000c 0x00000003 0x00000003
121 0x00000002 0x00000001 0x00000004 0x00000005
122 0x00000004 0x00000009 0x0000000d 0x0000059f
123 0x00000000 0x00000003 0x00000003 0x00000003
124 0x00000003 0x00000001 0x0000000b 0x000000c8
125 0x00000003 0x00000007 0x00000004 0x0000000f
126 0x00000002 0x00000000 0x00000000 0x00000002
127 0x00000000 0x00000000 0x00000083 0xa06204ae
128 0x007dc010 0x00000000 0x00000000 0x00000000
129 0x00000000 0x00000000 0x00000000 0x00000000 >;
130 };
131 emc-table@380000 {
132 reg = < 380000 >;
133 compatible = "nvidia,tegra20-emc-table";
134 clock-frequency = < 380000 >;
135 nvidia,emc-registers = < 0x00000017 0x0000004b
136 0x00000012 0x00000006 0x00000004 0x00000005
137 0x00000003 0x0000000c 0x00000006 0x00000006
138 0x00000003 0x00000001 0x00000004 0x00000005
139 0x00000004 0x00000009 0x0000000d 0x00000b5f
140 0x00000000 0x00000003 0x00000003 0x00000006
141 0x00000006 0x00000001 0x00000011 0x000000c8
142 0x00000003 0x0000000e 0x00000007 0x0000000f
143 0x00000002 0x00000000 0x00000000 0x00000002
144 0x00000000 0x00000000 0x00000083 0xe044048b
145 0x007d8010 0x00000000 0x00000000 0x00000000
146 0x00000000 0x00000000 0x00000000 0x00000000 >;
147 };
148 };
Anton Staffc3ab91f2012-04-17 09:01:34 +0000149
Allen Martinb7723f32013-01-16 13:12:24 +0000150 usb@c5000000 {
151 nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
152 dr_mode = "otg";
Anton Staffc3ab91f2012-04-17 09:01:34 +0000153 };
Simon Glass7cedd1812012-07-29 20:53:28 +0000154
Allen Martinb7723f32013-01-16 13:12:24 +0000155 usb@c5004000 {
156 status = "disabled";
Simon Glass7cedd1812012-07-29 20:53:28 +0000157 };
Simon Glass77139f52012-10-17 13:24:58 +0000158
Allen Martinb7723f32013-01-16 13:12:24 +0000159 sdhci@c8000400 {
Tom Warren126685a2013-02-21 12:31:29 +0000160 status = "okay";
161 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
Allen Martinb7723f32013-01-16 13:12:24 +0000162 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
163 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Tom Warren126685a2013-02-21 12:31:29 +0000164 bus-width = <4>;
Allen Martinb7723f32013-01-16 13:12:24 +0000165 };
166
167 sdhci@c8000600 {
Tom Warren126685a2013-02-21 12:31:29 +0000168 status = "okay";
169 bus-width = <8>;
Simon Glass77139f52012-10-17 13:24:58 +0000170 };
171
172 lcd_panel: panel {
173 /* Seaboard has 1366x768 */
174 clock = <70600000>;
175 xres = <1366>;
176 yres = <768>;
177 left-margin = <58>;
178 right-margin = <58>;
179 hsync-len = <58>;
180 lower-margin = <4>;
181 upper-margin = <4>;
182 vsync-len = <4>;
183 hsync-active-high;
184 nvidia,bits-per-pixel = <16>;
185 nvidia,pwm = <&pwm 2 0>;
186 nvidia,backlight-enable-gpios = <&gpio 28 0>; /* PD4 */
187 nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
188 nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
189 nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
190 nvidia,panel-timings = <400 4 203 17 15>;
191 };
Simon Glass6710b5b2012-02-27 10:52:39 +0000192};