blob: 2c98d2785030c8b159e16e82aae514d51810c4c1 [file] [log] [blame]
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +02001/*
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +02002 * (C) Copyright 2000-2004
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +02004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_ARCH(powerpc)
25ENTRY(_start_440)
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +020026
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020027SECTIONS
28{
29 /* Read-only sections, merged into text segment: */
30 . = + SIZEOF_HEADERS;
31 .interp : { *(.interp) }
32 .hash : { *(.hash) }
33 .dynsym : { *(.dynsym) }
34 .dynstr : { *(.dynstr) }
35 .rel.text : { *(.rel.text) }
36 .rela.text : { *(.rela.text) }
37 .rel.data : { *(.rel.data) }
38 .rela.data : { *(.rela.data) }
39 .rel.rodata : { *(.rel.rodata) }
40 .rela.rodata : { *(.rela.rodata) }
41 .rel.got : { *(.rel.got) }
42 .rela.got : { *(.rela.got) }
43 .rel.ctors : { *(.rel.ctors) }
44 .rela.ctors : { *(.rela.ctors) }
45 .rel.dtors : { *(.rel.dtors) }
46 .rela.dtors : { *(.rela.dtors) }
47 .rel.bss : { *(.rel.bss) }
48 .rela.bss : { *(.rela.bss) }
49 .rel.plt : { *(.rel.plt) }
50 .rela.plt : { *(.rela.plt) }
51 .init : { *(.init) }
52 .plt : { *(.plt) }
53 .text :
54 {
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +020055 /* WARNING - the following is hand-optimized to fit within */
56 /* the sector layout of our flash chips! XXX FIXME XXX */
57
58
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +020059 *(.text)
60 *(.fixup)
61 *(.got1)
62 }
63 _etext = .;
64 PROVIDE (etext = .);
65 .rodata :
66 {
67 *(.rodata)
68 *(.rodata1)
69 *(.rodata.str1.4)
70 *(.eh_frame)
71 }
72 .fini : { *(.fini) } =0
73 .ctors : { *(.ctors) }
74 .dtors : { *(.dtors) }
75
76 /* Read-write section, merged into data segment: */
77 . = (. + 0x00FF) & 0xFFFFFF00;
78 _erotext = .;
79 PROVIDE (erotext = .);
80 .reloc :
81 {
82 *(.got)
83 _GOT2_TABLE_ = .;
84 *(.got2)
85 _FIXUP_TABLE_ = .;
86 *(.fixup)
87 }
88 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
89 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
90
91 .data :
92 {
93 *(.data)
94 *(.data1)
95 *(.sdata)
96 *(.sdata2)
97 *(.dynamic)
98 CONSTRUCTORS
99 }
100 _edata = .;
101 PROVIDE (edata = .);
102
103 . = .;
104 __u_boot_cmd_start = .;
105 .u_boot_cmd : { *(.u_boot_cmd) }
106 __u_boot_cmd_end = .;
107
108
109 . = .;
110 __start___ex_table = .;
111 __ex_table : { *(__ex_table) }
112 __stop___ex_table = .;
113
114 . = ALIGN(256);
115 __init_begin = .;
116 .text.init : { *(.text.init) }
117 .data.init : { *(.data.init) }
118 . = ALIGN(256);
119 __init_end = .;
120
121 __bss_start = .;
122 .bss (NOLOAD) :
123 {
124 *(.sbss) *(.scommon)
125 *(.dynbss)
126 *(.bss)
127 *(COMMON)
128 }
Ricardo Ribalda Delgado01a00432008-07-21 20:30:07 +0200129
130 ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
131
Ricardo Ribalda Delgado086511f2008-07-17 12:47:09 +0200132 _end = . ;
133 PROVIDE (end = .);
134}