blob: 992b11f64351b5ca0be24194d7853a9c87dc28e1 [file] [log] [blame]
Tom Warrenf7dc4ac2014-01-24 12:46:18 -07001/*
2 * (C) Copyright 2013
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/* AS3722-PMIC-specific early init regs */
9
10#define AS3722_I2C_ADDR 0x80
11
12#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
13#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
14#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
15#define AS3722_SDCONTROL_REG 0x4D
16
17#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
18#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
19#define AS3722_LDCONTROL_REG 0x4E
20
Allen Martina6c7b462014-12-04 06:36:30 -070021#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG)
Stephen Warrene04bfda2014-03-25 11:39:33 -060022#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
23#else
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070024#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
Stephen Warrene04bfda2014-03-25 11:39:33 -060025#endif
Tom Warrenf7dc4ac2014-01-24 12:46:18 -070026#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
27
28#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
29#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
30
31#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
32#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
33
34#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
35#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
36
37#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
38#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
39
40#define I2C_SEND_2_BYTES 0x0A02
41
42void pmic_enable_cpu_vdd(void);