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Vipin KUMAR5b1b1882010-06-29 10:53:34 +05301/*
2 * (C) Copyright 2010
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05306 */
7
8/*
Simon Glass64dcd252015-04-05 16:07:40 -06009 * Designware ethernet IP driver for U-Boot
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053010 */
11
12#include <common.h>
Simon Glass75577ba2015-04-05 16:07:41 -060013#include <dm.h>
Simon Glass64dcd252015-04-05 16:07:40 -060014#include <errno.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053015#include <miiphy.h>
16#include <malloc.h>
Bin Meng8b7ee662015-09-11 03:24:35 -070017#include <pci.h>
Stefan Roeseef760252012-05-07 12:04:25 +020018#include <linux/compiler.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053019#include <linux/err.h>
20#include <asm/io.h>
21#include "designware.h"
22
Simon Glass75577ba2015-04-05 16:07:41 -060023DECLARE_GLOBAL_DATA_PTR;
24
Alexey Brodkin92a190a2014-01-22 20:54:06 +040025static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
26{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010027#ifdef CONFIG_DM_ETH
28 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
29 struct eth_mac_regs *mac_p = priv->mac_regs_p;
30#else
Alexey Brodkin92a190a2014-01-22 20:54:06 +040031 struct eth_mac_regs *mac_p = bus->priv;
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010032#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +040033 ulong start;
34 u16 miiaddr;
35 int timeout = CONFIG_MDIO_TIMEOUT;
36
37 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
38 ((reg << MIIREGSHIFT) & MII_REGMSK);
39
40 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
41
42 start = get_timer(0);
43 while (get_timer(start) < timeout) {
44 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
45 return readl(&mac_p->miidata);
46 udelay(10);
47 };
48
Simon Glass64dcd252015-04-05 16:07:40 -060049 return -ETIMEDOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040050}
51
52static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
53 u16 val)
54{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010055#ifdef CONFIG_DM_ETH
56 struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
57 struct eth_mac_regs *mac_p = priv->mac_regs_p;
58#else
Alexey Brodkin92a190a2014-01-22 20:54:06 +040059 struct eth_mac_regs *mac_p = bus->priv;
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010060#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +040061 ulong start;
62 u16 miiaddr;
Simon Glass64dcd252015-04-05 16:07:40 -060063 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040064
65 writel(val, &mac_p->miidata);
66 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
67 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
68
69 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
70
71 start = get_timer(0);
72 while (get_timer(start) < timeout) {
73 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
74 ret = 0;
75 break;
76 }
77 udelay(10);
78 };
79
80 return ret;
81}
82
Alexey Brodkin66d027e2016-06-27 13:17:51 +030083#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +010084static int dw_mdio_reset(struct mii_dev *bus)
85{
86 struct udevice *dev = bus->priv;
87 struct dw_eth_dev *priv = dev_get_priv(dev);
88 struct dw_eth_pdata *pdata = dev_get_platdata(dev);
89 int ret;
90
91 if (!dm_gpio_is_valid(&priv->reset_gpio))
92 return 0;
93
94 /* reset the phy */
95 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
96 if (ret)
97 return ret;
98
99 udelay(pdata->reset_delays[0]);
100
101 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
102 if (ret)
103 return ret;
104
105 udelay(pdata->reset_delays[1]);
106
107 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
108 if (ret)
109 return ret;
110
111 udelay(pdata->reset_delays[2]);
112
113 return 0;
114}
115#endif
116
117static int dw_mdio_init(const char *name, void *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400118{
119 struct mii_dev *bus = mdio_alloc();
120
121 if (!bus) {
122 printf("Failed to allocate MDIO bus\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600123 return -ENOMEM;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400124 }
125
126 bus->read = dw_mdio_read;
127 bus->write = dw_mdio_write;
Ben Whitten192bc692015-12-30 13:05:58 +0000128 snprintf(bus->name, sizeof(bus->name), "%s", name);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300129#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100130 bus->reset = dw_mdio_reset;
131#endif
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400132
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100133 bus->priv = priv;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400134
135 return mdio_register(bus);
136}
Vipin Kumar13edd172012-03-26 00:09:56 +0000137
Simon Glass64dcd252015-04-05 16:07:40 -0600138static void tx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530139{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530140 struct eth_dma_regs *dma_p = priv->dma_regs_p;
141 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
142 char *txbuffs = &priv->txbuffs[0];
143 struct dmamacdescr *desc_p;
144 u32 idx;
145
146 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
147 desc_p = &desc_table_p[idx];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200148 desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
149 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530150
151#if defined(CONFIG_DW_ALTDESCRIPTOR)
152 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
Marek Vasut2b261092015-12-20 03:59:23 +0100153 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
154 DESC_TXSTS_TXCHECKINSCTRL |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530155 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
156
157 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
158 desc_p->dmamac_cntl = 0;
159 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
160#else
161 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
162 desc_p->txrx_status = 0;
163#endif
164 }
165
166 /* Correcting the last pointer of the chain */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200167 desc_p->dmamac_next = (ulong)&desc_table_p[0];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530168
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400169 /* Flush all Tx buffer descriptors at once */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200170 flush_dcache_range((ulong)priv->tx_mac_descrtable,
171 (ulong)priv->tx_mac_descrtable +
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400172 sizeof(priv->tx_mac_descrtable));
173
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400175 priv->tx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530176}
177
Simon Glass64dcd252015-04-05 16:07:40 -0600178static void rx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530179{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530180 struct eth_dma_regs *dma_p = priv->dma_regs_p;
181 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
182 char *rxbuffs = &priv->rxbuffs[0];
183 struct dmamacdescr *desc_p;
184 u32 idx;
185
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400186 /* Before passing buffers to GMAC we need to make sure zeros
187 * written there right after "priv" structure allocation were
188 * flushed into RAM.
189 * Otherwise there's a chance to get some of them flushed in RAM when
190 * GMAC is already pushing data to RAM via DMA. This way incoming from
191 * GMAC data will be corrupted. */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200192 flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400193
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530194 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
195 desc_p = &desc_table_p[idx];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200196 desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
197 desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530198
199 desc_p->dmamac_cntl =
Marek Vasut2b261092015-12-20 03:59:23 +0100200 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530201 DESC_RXCTRL_RXCHAIN;
202
203 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
204 }
205
206 /* Correcting the last pointer of the chain */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200207 desc_p->dmamac_next = (ulong)&desc_table_p[0];
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530208
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400209 /* Flush all Rx buffer descriptors at once */
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200210 flush_dcache_range((ulong)priv->rx_mac_descrtable,
211 (ulong)priv->rx_mac_descrtable +
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400212 sizeof(priv->rx_mac_descrtable));
213
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400215 priv->rx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530216}
217
Simon Glass64dcd252015-04-05 16:07:40 -0600218static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530219{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530220 struct eth_mac_regs *mac_p = priv->mac_regs_p;
221 u32 macid_lo, macid_hi;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530222
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400223 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
224 (mac_id[3] << 24);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530225 macid_hi = mac_id[4] + (mac_id[5] << 8);
226
227 writel(macid_hi, &mac_p->macaddr0hi);
228 writel(macid_lo, &mac_p->macaddr0lo);
229
230 return 0;
231}
232
Simon Glass0ea38db2017-01-11 11:46:08 +0100233static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
234 struct phy_device *phydev)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400235{
236 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
237
238 if (!phydev->link) {
239 printf("%s: No link.\n", phydev->dev->name);
Simon Glass0ea38db2017-01-11 11:46:08 +0100240 return 0;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400241 }
242
243 if (phydev->speed != 1000)
244 conf |= MII_PORTSELECT;
Alexey Brodkinb884c3f2016-01-13 16:59:36 +0300245 else
246 conf &= ~MII_PORTSELECT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400247
248 if (phydev->speed == 100)
249 conf |= FES_100;
250
251 if (phydev->duplex)
252 conf |= FULLDPLXMODE;
253
254 writel(conf, &mac_p->conf);
255
256 printf("Speed: %d, %s duplex%s\n", phydev->speed,
257 (phydev->duplex) ? "full" : "half",
258 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Simon Glass0ea38db2017-01-11 11:46:08 +0100259
260 return 0;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400261}
262
Simon Glass64dcd252015-04-05 16:07:40 -0600263static void _dw_eth_halt(struct dw_eth_dev *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400264{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400265 struct eth_mac_regs *mac_p = priv->mac_regs_p;
266 struct eth_dma_regs *dma_p = priv->dma_regs_p;
267
268 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
270
271 phy_shutdown(priv->phydev);
272}
273
Simon Glasse72ced22017-01-11 11:46:10 +0100274int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530275{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530276 struct eth_mac_regs *mac_p = priv->mac_regs_p;
277 struct eth_dma_regs *dma_p = priv->dma_regs_p;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400278 unsigned int start;
Simon Glass64dcd252015-04-05 16:07:40 -0600279 int ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530280
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
Vipin Kumar13edd172012-03-26 00:09:56 +0000282
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400283 start = get_timer(0);
284 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
Alexey Brodkin875143f2015-01-13 17:10:24 +0300285 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
286 printf("DMA reset timeout\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600287 return -ETIMEDOUT;
Alexey Brodkin875143f2015-01-13 17:10:24 +0300288 }
Stefan Roeseef760252012-05-07 12:04:25 +0200289
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400290 mdelay(100);
291 };
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530292
Bin Mengf3edfd32015-06-15 18:40:19 +0800293 /*
294 * Soft reset above clears HW address registers.
295 * So we have to set it here once again.
296 */
297 _dw_write_hwaddr(priv, enetaddr);
298
Simon Glass64dcd252015-04-05 16:07:40 -0600299 rx_descs_init(priv);
300 tx_descs_init(priv);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530301
Ian Campbell49692c52014-05-08 22:26:35 +0100302 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530303
Sonic Zhangd2279222015-01-29 14:38:50 +0800304#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400305 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
306 &dma_p->opmode);
Sonic Zhangd2279222015-01-29 14:38:50 +0800307#else
308 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
309 &dma_p->opmode);
310#endif
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530311
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400312 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530313
Sonic Zhang2ddaf132015-01-29 13:37:31 +0800314#ifdef CONFIG_DW_AXI_BURST_LEN
315 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
316#endif
317
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400318 /* Start up the PHY */
Simon Glass64dcd252015-04-05 16:07:40 -0600319 ret = phy_startup(priv->phydev);
320 if (ret) {
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400321 printf("Could not initialize PHY %s\n",
322 priv->phydev->dev->name);
Simon Glass64dcd252015-04-05 16:07:40 -0600323 return ret;
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530324 }
325
Simon Glass0ea38db2017-01-11 11:46:08 +0100326 ret = dw_adjust_link(priv, mac_p, priv->phydev);
327 if (ret)
328 return ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530329
Simon Glassf63f28e2017-01-11 11:46:09 +0100330 return 0;
331}
332
Simon Glasse72ced22017-01-11 11:46:10 +0100333int designware_eth_enable(struct dw_eth_dev *priv)
Simon Glassf63f28e2017-01-11 11:46:09 +0100334{
335 struct eth_mac_regs *mac_p = priv->mac_regs_p;
336
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400337 if (!priv->phydev->link)
Simon Glass64dcd252015-04-05 16:07:40 -0600338 return -EIO;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530339
Armando Viscontiaa510052012-03-26 00:09:55 +0000340 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530341
342 return 0;
343}
344
Simon Glass64dcd252015-04-05 16:07:40 -0600345static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530346{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530347 struct eth_dma_regs *dma_p = priv->dma_regs_p;
348 u32 desc_num = priv->tx_currdescnum;
349 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200350 ulong desc_start = (ulong)desc_p;
351 ulong desc_end = desc_start +
Marek Vasut96cec172014-09-15 01:05:23 +0200352 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200353 ulong data_start = desc_p->dmamac_addr;
354 ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
Ian Campbell964ea7c2014-05-08 22:26:33 +0100355 /*
356 * Strictly we only need to invalidate the "txrx_status" field
357 * for the following check, but on some platforms we cannot
Marek Vasut96cec172014-09-15 01:05:23 +0200358 * invalidate only 4 bytes, so we flush the entire descriptor,
359 * which is 16 bytes in total. This is safe because the
360 * individual descriptors in the array are each aligned to
361 * ARCH_DMA_MINALIGN and padded appropriately.
Ian Campbell964ea7c2014-05-08 22:26:33 +0100362 */
Marek Vasut96cec172014-09-15 01:05:23 +0200363 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400364
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530365 /* Check if the descriptor is owned by CPU */
366 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
367 printf("CPU not owner of tx frame\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600368 return -EPERM;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530369 }
370
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200371 memcpy((void *)data_start, packet, length);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530372
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400373 /* Flush data to be sent */
Marek Vasut96cec172014-09-15 01:05:23 +0200374 flush_dcache_range(data_start, data_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400375
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530376#if defined(CONFIG_DW_ALTDESCRIPTOR)
377 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
Marek Vasut2b261092015-12-20 03:59:23 +0100378 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) &
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530379 DESC_TXCTRL_SIZE1MASK;
380
381 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
382 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
383#else
Marek Vasut2b261092015-12-20 03:59:23 +0100384 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) &
385 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530386 DESC_TXCTRL_TXFIRST;
387
388 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
389#endif
390
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400391 /* Flush modified buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200392 flush_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400393
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530394 /* Test the wrap-around condition. */
395 if (++desc_num >= CONFIG_TX_DESCR_NUM)
396 desc_num = 0;
397
398 priv->tx_currdescnum = desc_num;
399
400 /* Start the transmission */
401 writel(POLL_DATA, &dma_p->txpolldemand);
402
403 return 0;
404}
405
Simon Glass75577ba2015-04-05 16:07:41 -0600406static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530407{
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400408 u32 status, desc_num = priv->rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530409 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Simon Glass75577ba2015-04-05 16:07:41 -0600410 int length = -EAGAIN;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200411 ulong desc_start = (ulong)desc_p;
412 ulong desc_end = desc_start +
Marek Vasut96cec172014-09-15 01:05:23 +0200413 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200414 ulong data_start = desc_p->dmamac_addr;
415 ulong data_end;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530416
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400417 /* Invalidate entire buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200418 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400419
420 status = desc_p->txrx_status;
421
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530422 /* Check if the owner is the CPU */
423 if (!(status & DESC_RXSTS_OWNBYDMA)) {
424
Marek Vasut2b261092015-12-20 03:59:23 +0100425 length = (status & DESC_RXSTS_FRMLENMSK) >>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530426 DESC_RXSTS_FRMLENSHFT;
427
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400428 /* Invalidate received data */
Marek Vasut96cec172014-09-15 01:05:23 +0200429 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
430 invalidate_dcache_range(data_start, data_end);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200431 *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530432 }
433
Simon Glass75577ba2015-04-05 16:07:41 -0600434 return length;
435}
436
437static int _dw_free_pkt(struct dw_eth_dev *priv)
438{
439 u32 desc_num = priv->rx_currdescnum;
440 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200441 ulong desc_start = (ulong)desc_p;
442 ulong desc_end = desc_start +
Simon Glass75577ba2015-04-05 16:07:41 -0600443 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
444
445 /*
446 * Make the current descriptor valid again and go to
447 * the next one
448 */
449 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
450
451 /* Flush only status field - others weren't changed */
452 flush_dcache_range(desc_start, desc_end);
453
454 /* Test the wrap-around condition. */
455 if (++desc_num >= CONFIG_RX_DESCR_NUM)
456 desc_num = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530457 priv->rx_currdescnum = desc_num;
458
Simon Glass75577ba2015-04-05 16:07:41 -0600459 return 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530460}
461
Simon Glass64dcd252015-04-05 16:07:40 -0600462static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530463{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400464 struct phy_device *phydev;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300465 int mask = 0xffffffff, ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530466
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400467#ifdef CONFIG_PHY_ADDR
468 mask = 1 << CONFIG_PHY_ADDR;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530469#endif
470
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400471 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
472 if (!phydev)
Simon Glass64dcd252015-04-05 16:07:40 -0600473 return -ENODEV;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530474
Ian Campbell15e82e52014-04-28 20:14:05 +0100475 phy_connect_dev(phydev, dev);
476
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400477 phydev->supported &= PHY_GBIT_FEATURES;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300478 if (priv->max_speed) {
479 ret = phy_set_supported(phydev, priv->max_speed);
480 if (ret)
481 return ret;
482 }
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400483 phydev->advertising = phydev->supported;
484
485 priv->phydev = phydev;
486 phy_config(phydev);
487
Simon Glass64dcd252015-04-05 16:07:40 -0600488 return 0;
489}
490
Simon Glass75577ba2015-04-05 16:07:41 -0600491#ifndef CONFIG_DM_ETH
Simon Glass64dcd252015-04-05 16:07:40 -0600492static int dw_eth_init(struct eth_device *dev, bd_t *bis)
493{
Simon Glassf63f28e2017-01-11 11:46:09 +0100494 int ret;
495
Simon Glasse72ced22017-01-11 11:46:10 +0100496 ret = designware_eth_init(dev->priv, dev->enetaddr);
Simon Glassf63f28e2017-01-11 11:46:09 +0100497 if (!ret)
498 ret = designware_eth_enable(dev->priv);
499
500 return ret;
Simon Glass64dcd252015-04-05 16:07:40 -0600501}
502
503static int dw_eth_send(struct eth_device *dev, void *packet, int length)
504{
505 return _dw_eth_send(dev->priv, packet, length);
506}
507
508static int dw_eth_recv(struct eth_device *dev)
509{
Simon Glass75577ba2015-04-05 16:07:41 -0600510 uchar *packet;
511 int length;
512
513 length = _dw_eth_recv(dev->priv, &packet);
514 if (length == -EAGAIN)
515 return 0;
516 net_process_received_packet(packet, length);
517
518 _dw_free_pkt(dev->priv);
519
520 return 0;
Simon Glass64dcd252015-04-05 16:07:40 -0600521}
522
523static void dw_eth_halt(struct eth_device *dev)
524{
525 return _dw_eth_halt(dev->priv);
526}
527
528static int dw_write_hwaddr(struct eth_device *dev)
529{
530 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530531}
532
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400533int designware_initialize(ulong base_addr, u32 interface)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530534{
535 struct eth_device *dev;
536 struct dw_eth_dev *priv;
537
538 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
539 if (!dev)
540 return -ENOMEM;
541
542 /*
543 * Since the priv structure contains the descriptors which need a strict
544 * buswidth alignment, memalign is used to allocate memory
545 */
Ian Campbell1c848a22014-05-08 22:26:32 +0100546 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
547 sizeof(struct dw_eth_dev));
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530548 if (!priv) {
549 free(dev);
550 return -ENOMEM;
551 }
552
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200553 if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
554 printf("designware: buffers are outside DMA memory\n");
555 return -EINVAL;
556 }
557
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530558 memset(dev, 0, sizeof(struct eth_device));
559 memset(priv, 0, sizeof(struct dw_eth_dev));
560
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400561 sprintf(dev->name, "dwmac.%lx", base_addr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530562 dev->iobase = (int)base_addr;
563 dev->priv = priv;
564
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530565 priv->dev = dev;
566 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
567 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
568 DW_DMA_BASE_OFFSET);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530569
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530570 dev->init = dw_eth_init;
571 dev->send = dw_eth_send;
572 dev->recv = dw_eth_recv;
573 dev->halt = dw_eth_halt;
574 dev->write_hwaddr = dw_write_hwaddr;
575
576 eth_register(dev);
577
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400578 priv->interface = interface;
579
580 dw_mdio_init(dev->name, priv->mac_regs_p);
581 priv->bus = miiphy_get_dev_by_name(dev->name);
582
Simon Glass64dcd252015-04-05 16:07:40 -0600583 return dw_phy_init(priv, dev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530584}
Simon Glass75577ba2015-04-05 16:07:41 -0600585#endif
586
587#ifdef CONFIG_DM_ETH
588static int designware_eth_start(struct udevice *dev)
589{
590 struct eth_pdata *pdata = dev_get_platdata(dev);
Simon Glassf63f28e2017-01-11 11:46:09 +0100591 struct dw_eth_dev *priv = dev_get_priv(dev);
592 int ret;
Simon Glass75577ba2015-04-05 16:07:41 -0600593
Simon Glasse72ced22017-01-11 11:46:10 +0100594 ret = designware_eth_init(priv, pdata->enetaddr);
Simon Glassf63f28e2017-01-11 11:46:09 +0100595 if (ret)
596 return ret;
597 ret = designware_eth_enable(priv);
598 if (ret)
599 return ret;
600
601 return 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600602}
603
Simon Glasse72ced22017-01-11 11:46:10 +0100604int designware_eth_send(struct udevice *dev, void *packet, int length)
Simon Glass75577ba2015-04-05 16:07:41 -0600605{
606 struct dw_eth_dev *priv = dev_get_priv(dev);
607
608 return _dw_eth_send(priv, packet, length);
609}
610
Simon Glasse72ced22017-01-11 11:46:10 +0100611int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
Simon Glass75577ba2015-04-05 16:07:41 -0600612{
613 struct dw_eth_dev *priv = dev_get_priv(dev);
614
615 return _dw_eth_recv(priv, packetp);
616}
617
Simon Glasse72ced22017-01-11 11:46:10 +0100618int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
Simon Glass75577ba2015-04-05 16:07:41 -0600619{
620 struct dw_eth_dev *priv = dev_get_priv(dev);
621
622 return _dw_free_pkt(priv);
623}
624
Simon Glasse72ced22017-01-11 11:46:10 +0100625void designware_eth_stop(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600626{
627 struct dw_eth_dev *priv = dev_get_priv(dev);
628
629 return _dw_eth_halt(priv);
630}
631
Simon Glasse72ced22017-01-11 11:46:10 +0100632int designware_eth_write_hwaddr(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600633{
634 struct eth_pdata *pdata = dev_get_platdata(dev);
635 struct dw_eth_dev *priv = dev_get_priv(dev);
636
637 return _dw_write_hwaddr(priv, pdata->enetaddr);
638}
639
Bin Meng8b7ee662015-09-11 03:24:35 -0700640static int designware_eth_bind(struct udevice *dev)
641{
642#ifdef CONFIG_DM_PCI
643 static int num_cards;
644 char name[20];
645
646 /* Create a unique device name for PCI type devices */
647 if (device_is_on_pci_bus(dev)) {
648 sprintf(name, "eth_designware#%u", num_cards++);
649 device_set_name(dev, name);
650 }
651#endif
652
653 return 0;
654}
655
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100656int designware_eth_probe(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600657{
658 struct eth_pdata *pdata = dev_get_platdata(dev);
659 struct dw_eth_dev *priv = dev_get_priv(dev);
Bin Mengf0dc73c2015-09-03 05:37:29 -0700660 u32 iobase = pdata->iobase;
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200661 ulong ioaddr;
Simon Glass75577ba2015-04-05 16:07:41 -0600662 int ret;
663
Bin Meng8b7ee662015-09-11 03:24:35 -0700664#ifdef CONFIG_DM_PCI
665 /*
666 * If we are on PCI bus, either directly attached to a PCI root port,
667 * or via a PCI bridge, fill in platdata before we probe the hardware.
668 */
669 if (device_is_on_pci_bus(dev)) {
Bin Meng8b7ee662015-09-11 03:24:35 -0700670 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
671 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
Bin Meng6758a6c2016-02-02 05:58:00 -0800672 iobase = dm_pci_mem_to_phys(dev, iobase);
Bin Meng8b7ee662015-09-11 03:24:35 -0700673
674 pdata->iobase = iobase;
675 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
676 }
677#endif
678
Bin Mengf0dc73c2015-09-03 05:37:29 -0700679 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
Beniamino Galvani0e1a3e32016-05-08 08:30:15 +0200680 ioaddr = iobase;
681 priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
682 priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
Simon Glass75577ba2015-04-05 16:07:41 -0600683 priv->interface = pdata->phy_interface;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300684 priv->max_speed = pdata->max_speed;
Simon Glass75577ba2015-04-05 16:07:41 -0600685
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100686 dw_mdio_init(dev->name, dev);
Simon Glass75577ba2015-04-05 16:07:41 -0600687 priv->bus = miiphy_get_dev_by_name(dev->name);
688
689 ret = dw_phy_init(priv, dev);
690 debug("%s, ret=%d\n", __func__, ret);
691
692 return ret;
693}
694
Bin Meng5d2459f2015-10-07 21:32:38 -0700695static int designware_eth_remove(struct udevice *dev)
696{
697 struct dw_eth_dev *priv = dev_get_priv(dev);
698
699 free(priv->phydev);
700 mdio_unregister(priv->bus);
701 mdio_free(priv->bus);
702
703 return 0;
704}
705
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100706const struct eth_ops designware_eth_ops = {
Simon Glass75577ba2015-04-05 16:07:41 -0600707 .start = designware_eth_start,
708 .send = designware_eth_send,
709 .recv = designware_eth_recv,
710 .free_pkt = designware_eth_free_pkt,
711 .stop = designware_eth_stop,
712 .write_hwaddr = designware_eth_write_hwaddr,
713};
714
Sjoerd Simonsb9e08d02017-01-11 11:46:07 +0100715int designware_eth_ofdata_to_platdata(struct udevice *dev)
Simon Glass75577ba2015-04-05 16:07:41 -0600716{
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100717 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300718#ifdef CONFIG_DM_GPIO
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100719 struct dw_eth_dev *priv = dev_get_priv(dev);
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300720#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100721 struct eth_pdata *pdata = &dw_pdata->eth_pdata;
Simon Glass75577ba2015-04-05 16:07:41 -0600722 const char *phy_mode;
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300723 const fdt32_t *cell;
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300724#ifdef CONFIG_DM_GPIO
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100725 int reset_flags = GPIOD_IS_OUT;
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300726#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100727 int ret = 0;
Simon Glass75577ba2015-04-05 16:07:41 -0600728
729 pdata->iobase = dev_get_addr(dev);
730 pdata->phy_interface = -1;
731 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
732 if (phy_mode)
733 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
734 if (pdata->phy_interface == -1) {
735 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
736 return -EINVAL;
737 }
738
Alexey Brodkin6968ec92016-01-13 16:59:37 +0300739 pdata->max_speed = 0;
740 cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
741 if (cell)
742 pdata->max_speed = fdt32_to_cpu(*cell);
743
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300744#ifdef CONFIG_DM_GPIO
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100745 if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
746 "snps,reset-active-low"))
747 reset_flags |= GPIOD_ACTIVE_LOW;
748
749 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
750 &priv->reset_gpio, reset_flags);
751 if (ret == 0) {
752 ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
753 "snps,reset-delays-us", dw_pdata->reset_delays, 3);
754 } else if (ret == -ENOENT) {
755 ret = 0;
756 }
Alexey Brodkin66d027e2016-06-27 13:17:51 +0300757#endif
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100758
759 return ret;
Simon Glass75577ba2015-04-05 16:07:41 -0600760}
761
762static const struct udevice_id designware_eth_ids[] = {
763 { .compatible = "allwinner,sun7i-a20-gmac" },
Marek Vasutb9628592015-07-25 18:38:44 +0200764 { .compatible = "altr,socfpga-stmmac" },
Beniamino Galvanicfe25562016-08-16 11:49:50 +0200765 { .compatible = "amlogic,meson6-dwmac" },
Simon Glass75577ba2015-04-05 16:07:41 -0600766 { }
767};
768
Marek Vasut9f76f102015-07-25 18:42:34 +0200769U_BOOT_DRIVER(eth_designware) = {
Simon Glass75577ba2015-04-05 16:07:41 -0600770 .name = "eth_designware",
771 .id = UCLASS_ETH,
772 .of_match = designware_eth_ids,
773 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
Bin Meng8b7ee662015-09-11 03:24:35 -0700774 .bind = designware_eth_bind,
Simon Glass75577ba2015-04-05 16:07:41 -0600775 .probe = designware_eth_probe,
Bin Meng5d2459f2015-10-07 21:32:38 -0700776 .remove = designware_eth_remove,
Simon Glass75577ba2015-04-05 16:07:41 -0600777 .ops = &designware_eth_ops,
778 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
Sjoerd Simons90b7fc92016-02-28 22:24:55 +0100779 .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
Simon Glass75577ba2015-04-05 16:07:41 -0600780 .flags = DM_FLAG_ALLOC_PRIV_DMA,
781};
Bin Meng8b7ee662015-09-11 03:24:35 -0700782
783static struct pci_device_id supported[] = {
784 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
785 { }
786};
787
788U_BOOT_PCI_DEVICE(eth_designware, supported);
Simon Glass75577ba2015-04-05 16:07:41 -0600789#endif