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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* sdram_init.c - automatic memory sizing */
25
26#include <common.h>
27#include <74xx_7xx.h>
28#include <galileo/memory.h>
29#include <galileo/pci.h>
30#include <galileo/gt64260R.h>
31#include <net.h>
32
33#include "eth.h"
34#include "mpsc.h"
35#include "i2c.h"
36#include "64260.h"
37
38/* #define DEBUG */
39#define MAP_PCI
40
41#ifdef DEBUG
42#define DP(x) x
43#else
44#define DP(x)
45#endif
46
47#define GB (1 << 30)
48
49/* structure to store the relevant information about an sdram bank */
50typedef struct sdram_info {
51 uchar drb_size;
52 uchar registered, ecc;
53 uchar tpar;
54 uchar tras_clocks;
55 uchar burst_len;
56 uchar banks, slot;
57 int size; /* detected size, not from I2C but from dram_size() */
58} sdram_info_t;
59
60#ifdef DEBUG
61void dump_dimm_info(struct sdram_info *d)
62{
63 static const char *ecc_legend[]={""," Parity"," ECC"};
64 printf("dimm%s %sDRAM: %dMibytes:\n",
65 ecc_legend[d->ecc],
66 d->registered?"R":"",
67 (d->size>>20));
68 printf(" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
69 d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
70 d->banks, d->slot);
71}
72#endif
73
74static int
75memory_map_bank(unsigned int bankNo,
76 unsigned int bankBase,
77 unsigned int bankLength)
78{
79#ifdef DEBUG
80 if (bankLength > 0) {
81 printf("mapping bank %d at %08x - %08x\n",
82 bankNo, bankBase, bankBase + bankLength - 1);
83 } else {
84 printf("unmapping bank %d\n", bankNo);
85 }
86#endif
87
88 memoryMapBank(bankNo, bankBase, bankLength);
89
90 return 0;
91}
92
93#ifdef MAP_PCI
94static int
95memory_map_bank_pci(unsigned int bankNo,
96 unsigned int bankBase,
97 unsigned int bankLength)
98{
99 PCI_HOST host;
100 for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
101 const int features=
102 PREFETCH_ENABLE |
103 DELAYED_READ_ENABLE |
104 AGGRESSIVE_PREFETCH |
105 READ_LINE_AGGRESSIVE_PREFETCH |
106 READ_MULTI_AGGRESSIVE_PREFETCH |
107 MAX_BURST_4 |
108 PCI_NO_SWAP;
109
110 pciMapMemoryBank(host, bankNo, bankBase, bankLength);
111
112 pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
113 bankLength);
114
115 pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
116 }
117 return 0;
118}
119#endif
120
121/* ------------------------------------------------------------------------- */
122
123/* much of this code is based on (or is) the code in the pip405 port */
124/* thanks go to the authors of said port - Josh */
125
126
127/*
128 * translate ns.ns/10 coding of SPD timing values
129 * into 10 ps unit values
130 */
131static inline unsigned short
132NS10to10PS(unsigned char spd_byte)
133{
134 unsigned short ns, ns10;
135
136 /* isolate upper nibble */
137 ns = (spd_byte >> 4) & 0x0F;
138 /* isolate lower nibble */
139 ns10 = (spd_byte & 0x0F);
140
141 return(ns*100 + ns10*10);
142}
143
144/*
145 * translate ns coding of SPD timing values
146 * into 10 ps unit values
147 */
148static inline unsigned short
149NSto10PS(unsigned char spd_byte)
150{
151 return(spd_byte*100);
152}
153
154#ifdef CONFIG_ZUMA_V2
155static int
156check_dimm(uchar slot, sdram_info_t *info)
157{
wdenk8bde7f72003-06-27 21:31:46 +0000158 /* assume 2 dimms, 2 banks each 256M - we dont have an
wdenkc6097192002-11-03 00:24:07 +0000159 * dimm i2c so rely on the detection routines later */
160
161 memset(info, 0, sizeof(*info));
162
163 info->slot = slot;
164 info->banks = 2; /* Detect later */
165 info->registered = 0;
166 info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
167 but doesn't matter, both do same
168 thing in setup_sdram() */
169 info->tpar = 3;
170 info->tras_clocks = 5;
171 info->burst_len = 4;
172#ifdef CONFIG_ECC
173 info->ecc = 0; /* Detect later */
174#endif /* CONFIG_ECC */
175 return 0;
176}
177
wdenk12f34242003-09-02 22:48:03 +0000178#elif defined(CONFIG_P3G4)
179
180static int
181check_dimm(uchar slot, sdram_info_t *info)
182{
183 memset(info, 0, sizeof(*info));
184
185 if (slot)
186 return 0;
187
188 info->slot = slot;
189 info->banks = 1;
190 info->registered = 0;
191 info->drb_size = 4;
192 info->tpar = 3;
193 info->tras_clocks = 6;
194 info->burst_len = 4;
195#ifdef CONFIG_ECC
196 info->ecc = 2;
197#endif
198 return 0;
199}
200
201#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4*/
wdenkc6097192002-11-03 00:24:07 +0000202
203/* This code reads the SPD chip on the sdram and populates
204 * the array which is passed in with the relevant information */
205static int
206check_dimm(uchar slot, sdram_info_t *info)
207{
208 DECLARE_GLOBAL_DATA_PTR;
209 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
210 int ret;
211 uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
212 ulong tmemclk;
213 uchar trp_clocks, trcd_clocks;
214 uchar data[128];
215
216 get_clocks ();
217
wdenk8bde7f72003-06-27 21:31:46 +0000218 tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
wdenkc6097192002-11-03 00:24:07 +0000219
220#ifdef CONFIG_EVB64260_750CX
221 if (0 != slot) {
222 printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
223 printf(" called with slot=%d insetad!\n", slot);
224 return 0;
225 }
226#endif
227 DP(puts("before i2c read\n"));
228
229 ret = i2c_read(addr, 0, 128, data, 0);
230
231 DP(puts("after i2c read\n"));
232
233 /* zero all the values */
234 memset(info, 0, sizeof(*info));
235
236 if (ret) {
237 DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
238 return 0;
239 }
240
241 /* first, do some sanity checks */
242 if (data[2] != 0x4) {
243 printf("Not SDRAM in slot %d\n", slot);
244 return 0;
245 }
246
247 /* get various information */
248 rows = data[3];
249 cols = data[4];
250 info->banks = data[5];
251 sdram_banks = data[17];
252 width = data[13] & 0x7f;
253
254 DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
255
256 /* check if the memory is registered */
257 if (data[21] & (BIT1 | BIT4))
258 info->registered = 1;
259
260#ifdef CONFIG_ECC
261 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
262 info->ecc = (data[11] & 2) >> 1;
263#endif
264
265 /* bit 1 is CL2, bit 2 is CL3 */
266 supp_cal = (data[18] & 0x6) >> 1;
267
268 /* compute the relevant clock values */
269 trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk;
270 trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk;
271 info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk;
272
273 DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
274 trp_clocks, trcd_clocks, info->tras_clocks));
275
276 /* try a CAS latency of 3 first... */
277 cal_val = 0;
278 if (supp_cal & 3) {
279 if (NS10to10PS(data[9]) <= tmemclk)
280 cal_val = 3;
281 }
282
283 /* then 2... */
284 if (supp_cal & 2) {
285 if (NS10to10PS(data[23]) <= tmemclk)
286 cal_val = 2;
287 }
288
289 DP(printf("cal_val = %d\n", cal_val));
290
291 /* bummer, did't work... */
292 if (cal_val == 0) {
293 DP(printf("Couldn't find a good CAS latency\n"));
294 return 0;
295 }
296
297 /* get the largest delay -- these values need to all be the same
298 * see Res#6 */
299 info->tpar = cal_val;
300 if (trp_clocks > info->tpar)
301 info->tpar = trp_clocks;
302 if (trcd_clocks > info->tpar)
303 info->tpar = trcd_clocks;
304
305 DP(printf("tpar set to: %d\n", info->tpar));
306
307#ifdef CFG_BROKEN_CL2
308 if (info->tpar == 2){
309 info->tpar = 3;
wdenk8bde7f72003-06-27 21:31:46 +0000310 DP(printf("tpar fixed-up to: %d\n", info->tpar));
wdenkc6097192002-11-03 00:24:07 +0000311 }
312#endif
313 /* compute the module DRB size */
314 info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
315
316 DP(printf("drb_size set to: %d\n", info->drb_size));
317
318 /* find the burst len */
319 info->burst_len = data[16] & 0xf;
320 if ((info->burst_len & 8) == 8) {
321 info->burst_len = 1;
322 } else if ((info->burst_len & 4) == 4) {
323 info->burst_len = 0;
324 } else {
325 return 0;
326 }
327
328 info->slot = slot;
329 return 0;
330}
331#endif /* ! CONFIG_ZUMA_V2 */
332
333static int
334setup_sdram_common(sdram_info_t info[2])
335{
wdenk8bde7f72003-06-27 21:31:46 +0000336 ulong tmp;
wdenkc6097192002-11-03 00:24:07 +0000337 int tpar=2, tras_clocks=5, registered=1, ecc=2;
338
339 if(!info[0].banks && !info[1].banks) return 0;
340
341 if(info[0].banks) {
342 if(info[0].tpar>tpar) tpar=info[0].tpar;
343 if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
344 if(!info[0].registered) registered=0;
345 if(info[0].ecc!=2) ecc=0;
346 }
347
348 if(info[1].banks) {
349 if(info[1].tpar>tpar) tpar=info[1].tpar;
350 if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
351 if(!info[1].registered) registered=0;
352 if(info[1].ecc!=2) ecc=0;
353 }
354
355 /* SDRAM configuration */
356 tmp = GTREGREAD(SDRAM_CONFIGURATION);
357
358 /* Turn on physical interleave if both DIMMs
359 * have even numbers of banks. */
360 if( (info[0].banks == 0 || info[0].banks == 2) &&
361 (info[1].banks == 0 || info[1].banks == 2) ) {
362 /* physical interleave on */
363 tmp &= ~(1 << 15);
364 } else {
365 /* physical interleave off */
366 tmp |= (1 << 15);
367 }
368
369 tmp |= (registered << 17);
370
371 /* Use buffer 1 to return read data to the CPU
372 * See Res #12 */
373 tmp |= (1 << 26);
374
375 GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
376 DP(printf("SDRAM config: %08x\n",
377 GTREGREAD(SDRAM_CONFIGURATION)));
378
379 /* SDRAM timing */
380 tmp = (((tpar == 3) ? 2 : 1) |
381 (((tpar == 3) ? 2 : 1) << 2) |
382 (((tpar == 3) ? 2 : 1) << 4) |
383 (tras_clocks << 8));
384
385#ifdef CONFIG_ECC
386 /* Setup ECC */
387 if (ecc == 2) tmp |= 1<<13;
388#endif /* CONFIG_ECC */
389
390 GT_REG_WRITE(SDRAM_TIMING, tmp);
391 DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
392 GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
393
394 /* SDRAM address decode register */
395 /* program this with the default value */
396 GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
397 DP(printf("SDRAM decode: %08x\n",
398 GTREGREAD(SDRAM_ADDRESS_DECODE)));
399
400 return 0;
401}
402
403/* sets up the GT properly with information passed in */
404static int
405setup_sdram(sdram_info_t *info)
406{
407 ulong tmp, check;
408 ulong *addr = 0;
409 int i;
410
411 /* sanity checking */
412 if (! info->banks) return 0;
413
414 /* ---------------------------- */
415 /* Program the GT with the discovered data */
416
417 /* bank parameters */
418 tmp = (0xf<<16); /* leave all virt bank pages open */
419
420 DP(printf("drb_size: %d\n", info->drb_size));
421 switch (info->drb_size) {
422 case 1:
423 tmp |= (1 << 14);
424 break;
425 case 4:
426 case 8:
427 tmp |= (2 << 14);
428 break;
429 case 16:
430 case 32:
431 tmp |= (3 << 14);
432 break;
433 default:
434 printf("Error in dram size calculation\n");
435 return 1;
436 }
437
438 /* SDRAM bank parameters */
439 /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
440 GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
441 GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
442 DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
443
444 /* set the SDRAM configuration for each bank */
445 for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
446 DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
447
448 /* map the bank */
449 memory_map_bank(i, 0, GB/4);
450
451 /* set SDRAM mode */
452 GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3);
453 check = GTREGREAD(SDRAM_OPERATION_MODE);
454
455 /* dummy write */
456 *addr = 0;
457
458 /* wait for the command to complete */
459 while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0)
460 ;
461
462 /* switch back to normal operation mode */
463 GT_REG_WRITE(SDRAM_OPERATION_MODE, 0);
464 check = GTREGREAD(SDRAM_OPERATION_MODE);
465
466 /* unmap the bank */
467 memory_map_bank(i, 0, 0);
468 DP(printf("*** MRS cycle for bank %d done ***\n", i));
469 }
470
471 return 0;
472}
473
474/*
475 * Check memory range for valid RAM. A simple memory test determines
476 * the actually available RAM size between addresses `base' and
477 * `base + maxsize'. Some (not all) hardware errors are detected:
478 * - short between address lines
479 * - short between data lines
480 */
481static long int
482dram_size(long int *base, long int maxsize)
483{
484 volatile long int *addr, *b=base;
485 long int cnt, val, save1, save2;
486
487#define STARTVAL (1<<20) /* start test at 1M */
488 for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
489 addr = base + cnt; /* pointer arith! */
490
491 save1=*addr; /* save contents of addr */
492 save2=*b; /* save contents of base */
493
494 *addr=cnt; /* write cnt to addr */
495 *b=0; /* put null at base */
496
497 /* check at base address */
498 if ((*b) != 0) {
499 *addr=save1; /* restore *addr */
500 *b=save2; /* restore *b */
501 return (0);
502 }
503 val = *addr; /* read *addr */
504
505 *addr=save1;
506 *b=save2;
507
508 if (val != cnt) {
509 /* fix boundary condition.. STARTVAL means zero */
510 if(cnt==STARTVAL/sizeof(long)) cnt=0;
511 return (cnt * sizeof(long));
512 }
513 }
514 return maxsize;
515}
516
517/* ------------------------------------------------------------------------- */
518
519/* U-Boot interface function to SDRAM init - this is where all the
520 * controlling logic happens */
521long int
522initdram(int board_type)
523{
524 ulong checkbank[4] = { [0 ... 3] = 0 };
525 int bank_no;
wdenk8bde7f72003-06-27 21:31:46 +0000526 ulong total;
wdenkc6097192002-11-03 00:24:07 +0000527 int nhr;
528 sdram_info_t dimm_info[2];
529
530
531 /* first, use the SPD to get info about the SDRAM */
532
533 /* check the NHR bit and skip mem init if it's already done */
534 nhr = get_hid0() & (1 << 16);
535
536 if (nhr) {
537 printf("Skipping SDRAM setup due to NHR bit being set\n");
538 } else {
539 /* DIMM0 */
540 check_dimm(0, &dimm_info[0]);
541
542 /* DIMM1 */
543#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
544 check_dimm(1, &dimm_info[1]);
545#else /* CONFIG_EVB64260_750CX */
546 memset(&dimm_info[1], 0, sizeof(sdram_info_t));
547#endif
548
549 /* unmap all banks */
550 memory_map_bank(0, 0, 0);
551 memory_map_bank(1, 0, 0);
552 memory_map_bank(2, 0, 0);
553 memory_map_bank(3, 0, 0);
554
555 /* Now, program the GT with the correct values */
556 if (setup_sdram_common(dimm_info)) {
557 printf("Setup common failed.\n");
558 }
559
560 if (setup_sdram(&dimm_info[0])) {
561 printf("Setup for DIMM1 failed.\n");
562 }
563
564 if (setup_sdram(&dimm_info[1])) {
565 printf("Setup for DIMM2 failed.\n");
566 }
567
568 /* set the NHR bit */
569 set_hid0(get_hid0() | (1 << 16));
570 }
571 /* next, size the SDRAM banks */
572
573 total = 0;
574 if (dimm_info[0].banks > 0) checkbank[0] = 1;
575 if (dimm_info[0].banks > 1) checkbank[1] = 1;
576 if (dimm_info[0].banks > 2)
577 printf("Error, SPD claims DIMM1 has >2 banks\n");
578
579 if (dimm_info[1].banks > 0) checkbank[2] = 1;
580 if (dimm_info[1].banks > 1) checkbank[3] = 1;
581 if (dimm_info[1].banks > 2)
582 printf("Error, SPD claims DIMM2 has >2 banks\n");
583
584 /* Generic dram sizer: works even if we don't have i2c DIMMs,
585 * as long as the timing settings are more or less correct */
586
587 /*
588 * pass 1: size all the banks, using first bat (0-256M)
589 * limitation: we only support 256M per bank due to
590 * us only having 1 BAT for all DRAM
591 */
592 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
593 /* skip over banks that are not populated */
594 if (! checkbank[bank_no])
595 continue;
596
597 DP(printf("checking bank %d\n", bank_no));
598
599 memory_map_bank(bank_no, 0, GB/4);
600 checkbank[bank_no] = dram_size(NULL, GB/4);
601 memory_map_bank(bank_no, 0, 0);
602
603 DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
604 }
605
606 /*
607 * pass 2: contiguously map each bank into physical address
608 * space.
609 */
610 dimm_info[0].banks=dimm_info[1].banks=0;
611 for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
612 if(!checkbank[bank_no]) continue;
613
614 dimm_info[bank_no/2].banks++;
615 dimm_info[bank_no/2].size+=checkbank[bank_no];
616
617 memory_map_bank(bank_no, total, checkbank[bank_no]);
618#ifdef MAP_PCI
619 memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
620#endif
621 total += checkbank[bank_no];
622 }
623
624#ifdef CONFIG_ECC
625#ifdef CONFIG_ZUMA_V2
626 /*
627 * We always enable ECC when bank 2 and 3 are unpopulated
628 * If we 2 or 3 are populated, we CAN'T support ECC.
629 * (Zuma boards only support ECC in banks 0 and 1; assume that
630 * in that configuration, ECC chips are mounted, even for stacked
631 * chips)
632 */
633 if (checkbank[2]==0 && checkbank[3]==0) {
wdenk8bde7f72003-06-27 21:31:46 +0000634 dimm_info[0].ecc=2;
wdenkc6097192002-11-03 00:24:07 +0000635 GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
636 /* TODO: do we have to run MRS cycles again? */
637 }
638#endif /* CONFIG_ZUMA_V2 */
639
640 if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
641 puts("[ECC] ");
642 }
643#endif /* CONFIG_ECC */
644
645#ifdef DEBUG
646 dump_dimm_info(&dimm_info[0]);
647 dump_dimm_info(&dimm_info[1]);
648#endif
649 /* TODO: return at MOST 256M? */
wdenk8bde7f72003-06-27 21:31:46 +0000650 /* return total > GB/4 ? GB/4 : total; */
wdenkc6097192002-11-03 00:24:07 +0000651 return total;
652}