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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Mugunthan V Ndadf3132015-12-24 16:08:07 +05302/*
3 * TI OMAP timer driver
4 *
5 * Copyright (C) 2015, Texas Instruments, Incorporated
Mugunthan V Ndadf3132015-12-24 16:08:07 +05306 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <timer.h>
12#include <asm/io.h>
13#include <asm/arch/clock.h>
Tom Rini12f613c2022-05-12 17:22:26 -040014#include <asm/omap_common.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Mugunthan V Ndadf3132015-12-24 16:08:07 +053016
Mugunthan V Ndadf3132015-12-24 16:08:07 +053017/* Timer register bits */
18#define TCLR_START BIT(0) /* Start=1 */
19#define TCLR_AUTO_RELOAD BIT(1) /* Auto reload */
20#define TCLR_PRE_EN BIT(5) /* Pre-scaler enable */
21#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
22
Mugunthan V Ndadf3132015-12-24 16:08:07 +053023struct omap_gptimer_regs {
24 unsigned int tidr; /* offset 0x00 */
25 unsigned char res1[12];
26 unsigned int tiocp_cfg; /* offset 0x10 */
27 unsigned char res2[12];
28 unsigned int tier; /* offset 0x20 */
29 unsigned int tistatr; /* offset 0x24 */
30 unsigned int tistat; /* offset 0x28 */
31 unsigned int tisr; /* offset 0x2c */
32 unsigned int tcicr; /* offset 0x30 */
33 unsigned int twer; /* offset 0x34 */
34 unsigned int tclr; /* offset 0x38 */
35 unsigned int tcrr; /* offset 0x3c */
36 unsigned int tldr; /* offset 0x40 */
37 unsigned int ttgr; /* offset 0x44 */
38 unsigned int twpc; /* offset 0x48 */
39 unsigned int tmar; /* offset 0x4c */
40 unsigned int tcar1; /* offset 0x50 */
41 unsigned int tscir; /* offset 0x54 */
42 unsigned int tcar2; /* offset 0x58 */
43};
44
45/* Omap Timer Priv */
46struct omap_timer_priv {
47 struct omap_gptimer_regs *regs;
48};
49
Sean Anderson8af7bb92020-10-07 14:37:44 -040050static u64 omap_timer_get_count(struct udevice *dev)
Mugunthan V Ndadf3132015-12-24 16:08:07 +053051{
52 struct omap_timer_priv *priv = dev_get_priv(dev);
53
Sean Anderson8af7bb92020-10-07 14:37:44 -040054 return timer_conv_64(readl(&priv->regs->tcrr));
Mugunthan V Ndadf3132015-12-24 16:08:07 +053055}
56
57static int omap_timer_probe(struct udevice *dev)
58{
59 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
60 struct omap_timer_priv *priv = dev_get_priv(dev);
61
Lokesh Vutla84b42212018-08-16 18:26:55 +053062 if (!uc_priv->clock_rate)
Dario Binacchi11326f32020-12-30 00:16:22 +010063 uc_priv->clock_rate = V_SCLK;
64
Tom Rini12f613c2022-05-12 17:22:26 -040065 uc_priv->clock_rate /= (2 << SYS_PTV);
Mugunthan V Ndadf3132015-12-24 16:08:07 +053066
67 /* start the counter ticking up, reload value on overflow */
68 writel(0, &priv->regs->tldr);
Lokesh Vutla3ee15a52018-08-16 18:26:54 +053069 writel(0, &priv->regs->tcrr);
Mugunthan V Ndadf3132015-12-24 16:08:07 +053070 /* enable timer */
Tom Rini12f613c2022-05-12 17:22:26 -040071 writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
Mugunthan V Ndadf3132015-12-24 16:08:07 +053072 TCLR_START, &priv->regs->tclr);
73
74 return 0;
75}
76
Simon Glassd1998a92020-12-03 16:55:21 -070077static int omap_timer_of_to_plat(struct udevice *dev)
Mugunthan V Ndadf3132015-12-24 16:08:07 +053078{
79 struct omap_timer_priv *priv = dev_get_priv(dev);
80
Masahiro Yamada25484932020-07-17 14:36:48 +090081 priv->regs = map_physmem(dev_read_addr(dev),
Lokesh Vutla871ca262016-03-05 16:40:32 +053082 sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
Mugunthan V Ndadf3132015-12-24 16:08:07 +053083
84 return 0;
85}
86
Christian Gmeinere660cfa2021-12-16 10:57:29 +010087#if CONFIG_IS_ENABLED(BOOTSTAGE)
88ulong timer_get_boot_us(void)
89{
90 u64 ticks = 0;
91 u32 rate = 1;
92 u64 us;
93 int ret;
94
95 ret = dm_timer_init();
96 if (!ret) {
97 /* The timer is available */
98 rate = timer_get_rate(gd->timer);
99 timer_get_count(gd->timer, &ticks);
100 } else {
101 return 0;
102 }
103
104 us = (ticks * 1000) / rate;
105 return us;
106}
107#endif
Mugunthan V Ndadf3132015-12-24 16:08:07 +0530108
109static const struct timer_ops omap_timer_ops = {
110 .get_count = omap_timer_get_count,
111};
112
113static const struct udevice_id omap_timer_ids[] = {
114 { .compatible = "ti,am335x-timer" },
115 { .compatible = "ti,am4372-timer" },
116 { .compatible = "ti,omap5430-timer" },
117 {}
118};
119
120U_BOOT_DRIVER(omap_timer) = {
121 .name = "omap_timer",
122 .id = UCLASS_TIMER,
123 .of_match = omap_timer_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700124 .of_to_plat = omap_timer_of_to_plat,
Simon Glass41575d82020-12-03 16:55:17 -0700125 .priv_auto = sizeof(struct omap_timer_priv),
Mugunthan V Ndadf3132015-12-24 16:08:07 +0530126 .probe = omap_timer_probe,
127 .ops = &omap_timer_ops,
Mugunthan V Ndadf3132015-12-24 16:08:07 +0530128};