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Mingkai Huf3a8e2b2015-10-26 19:47:52 +08001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1043ARDB_H__
8#define __LS1043ARDB_H__
9
10#include "ls1043a_common.h"
11
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080012#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
Gong Qianyu3ad44722015-10-26 19:47:53 +080013#define CONFIG_SYS_TEXT_BASE 0x82000000
14#else
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080015#define CONFIG_SYS_TEXT_BASE 0x60100000
Gong Qianyu3ad44722015-10-26 19:47:53 +080016#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080017
18#define CONFIG_SYS_CLK_FREQ 100000000
19#define CONFIG_DDR_CLK_FREQ 100000000
20
21#define CONFIG_LAYERSCAPE_NS_ACCESS
22#define CONFIG_MISC_INIT_R
23
24#define CONFIG_DIMM_SLOTS_PER_CTLR 1
25/* Physical Memory Map */
26#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Shaohui Xiee994ddd2015-11-23 15:23:48 +080027#define CONFIG_NR_DRAM_BANKS 2
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080028
29#define CONFIG_SYS_SPD_BUS_NUM 0
30
31#define CONFIG_FSL_DDR_BIST
Hou Zhiqiangdc760ae2017-02-06 11:29:00 +080032#ifndef CONFIG_SPL
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080033#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
Hou Zhiqiangdc760ae2017-02-06 11:29:00 +080034#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080035#define CONFIG_SYS_DDR_RAW_TIMING
36#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
37#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38
Gong Qianyu3ad44722015-10-26 19:47:53 +080039#ifdef CONFIG_RAMBOOT_PBL
40#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
41#endif
42
43#ifdef CONFIG_NAND_BOOT
44#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
45#endif
46
Gong Qianyuc7ca8b02015-10-26 19:47:56 +080047#ifdef CONFIG_SD_BOOT
48#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
49#endif
50
Mingkai Huf3a8e2b2015-10-26 19:47:52 +080051/*
52 * NOR Flash Definitions
53 */
54#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
55#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
56#define CONFIG_SYS_NOR_CSPR \
57 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
58 CSPR_PORT_SIZE_16 | \
59 CSPR_MSEL_NOR | \
60 CSPR_V)
61
62/* NOR Flash Timing Params */
63#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
64 CSOR_NOR_TRHZ_80)
65#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
66 FTIM0_NOR_TEADC(0x1) | \
67 FTIM0_NOR_TAVDS(0x0) | \
68 FTIM0_NOR_TEAHC(0xc))
69#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
70 FTIM1_NOR_TRAD_NOR(0xb) | \
71 FTIM1_NOR_TSEQRAD_NOR(0x9))
72#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
73 FTIM2_NOR_TCH(0x4) | \
74 FTIM2_NOR_TWPH(0x8) | \
75 FTIM2_NOR_TWP(0x10))
76#define CONFIG_SYS_NOR_FTIM3 0
77#define CONFIG_SYS_IFC_CCR 0x01000000
78
79#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
80#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
81#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
82#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
83
84#define CONFIG_SYS_FLASH_EMPTY_INFO
85#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
86
87#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
88#define CONFIG_SYS_WRITE_SWAPPED_DATA
89
90/*
91 * NAND Flash Definitions
92 */
93#define CONFIG_NAND_FSL_IFC
94
95#define CONFIG_SYS_NAND_BASE 0x7e800000
96#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
97
98#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
99#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
100 | CSPR_PORT_SIZE_8 \
101 | CSPR_MSEL_NAND \
102 | CSPR_V)
103#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
104#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
105 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
106 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
107 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
108 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
109 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
110 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
111
112#define CONFIG_SYS_NAND_ONFI_DETECTION
113
114#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
115 FTIM0_NAND_TWP(0x18) | \
116 FTIM0_NAND_TWCHT(0x7) | \
117 FTIM0_NAND_TWH(0xa))
118#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
119 FTIM1_NAND_TWBE(0x39) | \
120 FTIM1_NAND_TRR(0xe) | \
121 FTIM1_NAND_TRP(0x18))
122#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
123 FTIM2_NAND_TREH(0xa) | \
124 FTIM2_NAND_TWHRE(0x1e))
125#define CONFIG_SYS_NAND_FTIM3 0x0
126
127#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
128#define CONFIG_SYS_MAX_NAND_DEVICE 1
129#define CONFIG_MTD_NAND_VERIFY_WRITE
130#define CONFIG_CMD_NAND
131
132#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
133
Gong Qianyu3ad44722015-10-26 19:47:53 +0800134#ifdef CONFIG_NAND_BOOT
135#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
136#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
137#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
138#endif
139
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800140/*
141 * CPLD
142 */
143#define CONFIG_SYS_CPLD_BASE 0x7fb00000
144#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
145
146#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
147#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
148 CSPR_PORT_SIZE_8 | \
149 CSPR_MSEL_GPCM | \
150 CSPR_V)
151#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
152#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
153 CSOR_NOR_NOR_MODE_AVD_NOR | \
154 CSOR_NOR_TRHZ_80)
155
156/* CPLD Timing parameters for IFC GPCM */
157#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
158 FTIM0_GPCM_TEADC(0xf) | \
159 FTIM0_GPCM_TEAHC(0xf))
160#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
161 FTIM1_GPCM_TRAD(0x3f))
162#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
163 FTIM2_GPCM_TCH(0xf) | \
164 FTIM2_GPCM_TWP(0xff))
165#define CONFIG_SYS_CPLD_FTIM3 0x0
166
167/* IFC Timing Params */
Gong Qianyu3ad44722015-10-26 19:47:53 +0800168#ifdef CONFIG_NAND_BOOT
169#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
170#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
171#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
172#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
173#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
174#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
175#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
176#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
177
178#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
179#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
180#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
181#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
182#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
183#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
184#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
185#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
186#else
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800187#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
188#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
189#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
190#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
191#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
192#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
193#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
194#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
195
196#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
197#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
198#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
199#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
200#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
201#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
202#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
203#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Gong Qianyu3ad44722015-10-26 19:47:53 +0800204#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800205
206#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
207#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
208#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
209#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
210#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
211#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
212#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
213#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
214
215/* EEPROM */
216#define CONFIG_ID_EEPROM
217#define CONFIG_SYS_I2C_EEPROM_NXID
218#define CONFIG_SYS_EEPROM_BUS_NUM 0
219#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
220#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
221#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
222#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
223
224/*
225 * Environment
226 */
Gong Qianyu3ad44722015-10-26 19:47:53 +0800227#define CONFIG_ENV_OVERWRITE
228
229#if defined(CONFIG_NAND_BOOT)
230#define CONFIG_ENV_IS_IN_NAND
231#define CONFIG_ENV_SIZE 0x2000
232#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
Gong Qianyuc7ca8b02015-10-26 19:47:56 +0800233#elif defined(CONFIG_SD_BOOT)
234#define CONFIG_ENV_OFFSET (1024 * 1024)
235#define CONFIG_ENV_IS_IN_MMC
236#define CONFIG_SYS_MMC_ENV_DEV 0
237#define CONFIG_ENV_SIZE 0x2000
Gong Qianyu3ad44722015-10-26 19:47:53 +0800238#else
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800239#define CONFIG_ENV_IS_IN_FLASH
240#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
241#define CONFIG_ENV_SECT_SIZE 0x20000
242#define CONFIG_ENV_SIZE 0x20000
Gong Qianyu3ad44722015-10-26 19:47:53 +0800243#endif
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800244
Shaohui Xiee8297342015-10-26 19:47:54 +0800245/* FMan */
246#ifdef CONFIG_SYS_DPAA_FMAN
247#define CONFIG_FMAN_ENET
Shaohui Xiee8297342015-10-26 19:47:54 +0800248#define CONFIG_PHYLIB
249#define CONFIG_PHYLIB_10G
250#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
251
252#define CONFIG_PHY_VITESSE
253#define CONFIG_PHY_REALTEK
254#define CONFIG_PHY_AQUANTIA
Shaohui Xie79425502016-04-29 22:07:21 +0800255#define AQR105_IRQ_MASK 0x40000000
Shaohui Xiee8297342015-10-26 19:47:54 +0800256
257#define RGMII_PHY1_ADDR 0x1
258#define RGMII_PHY2_ADDR 0x2
259
260#define QSGMII_PORT1_PHY_ADDR 0x4
261#define QSGMII_PORT2_PHY_ADDR 0x5
262#define QSGMII_PORT3_PHY_ADDR 0x6
263#define QSGMII_PORT4_PHY_ADDR 0x7
264
265#define FM1_10GEC1_PHY_ADDR 0x1
266
267#define CONFIG_ETHPRIME "FM1@DTSEC3"
268#endif
269
Zhao Qiangd3e6d302016-02-05 10:04:17 +0800270/* QE */
271#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
272 !defined(CONFIG_QSPI_BOOT)
273#define CONFIG_U_QE
274#endif
275#define CONFIG_SYS_QE_FW_ADDR 0x60600000
276
Gong Qianyu70231002015-11-11 17:58:40 +0800277/* USB */
278#define CONFIG_HAS_FSL_XHCI_USB
279#ifdef CONFIG_HAS_FSL_XHCI_USB
Gong Qianyu70231002015-11-11 17:58:40 +0800280#define CONFIG_USB_XHCI_FSL
Gong Qianyu70231002015-11-11 17:58:40 +0800281#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
282#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
Gong Qianyu70231002015-11-11 17:58:40 +0800283#endif
284
Po Liubc323b32016-05-18 10:09:38 +0800285/* SATA */
286#define CONFIG_LIBATA
287#define CONFIG_SCSI_AHCI
288#define CONFIG_CMD_SCSI
289#ifndef CONFIG_CMD_FAT
290#define CONFIG_CMD_FAT
291#endif
292#ifndef CONFIG_CMD_EXT2
293#define CONFIG_CMD_EXT2
294#endif
Po Liubc323b32016-05-18 10:09:38 +0800295#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
296#define CONFIG_SYS_SCSI_MAX_LUN 2
297#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
298 CONFIG_SYS_SCSI_MAX_LUN)
299#define SCSI_VEND_ID 0x1b4b
300#define SCSI_DEV_ID 0x9170
301#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
Po Liubc323b32016-05-18 10:09:38 +0800302
Aneesh Bansal9711f522015-12-08 13:54:29 +0530303#include <asm/fsl_secure_boot.h>
304
Mingkai Huf3a8e2b2015-10-26 19:47:52 +0800305#endif /* __LS1043ARDB_H__ */