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wdenk5b1d7132002-11-03 00:07:02 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenk5b1d7132002-11-03 00:07:02 +000024/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
25 * U-Boot port on RPXlite board
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define RPXLite_50MHz
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#undef CONFIG_MPC860
39#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
40#define CONFIG_RPXLITE 1
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
46#if 0
47#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48#else
49#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50#endif
51
wdenk5b1d7132002-11-03 00:07:02 +000052#undef CONFIG_BOOTARGS
53#define CONFIG_BOOTCOMMAND \
54 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk5b1d7132002-11-03 00:07:02 +000057 "bootm"
58
59#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
61
Wolfgang Denkf47b6612006-03-12 01:48:55 +010062#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
wdenk5b1d7132002-11-03 00:07:02 +000063#undef CONFIG_WATCHDOG /* watchdog disabled */
64
65#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
66
67/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
68#include <cmd_confdefs.h>
69
70/*
71 * Miscellaneous configurable options
72 */
73#define CFG_LONGHELP /* undef to save memory */
74#define CFG_PROMPT "=> " /* Monitor Command Prompt */
75#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
76#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
77#else
78#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
79#endif
80#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
81#define CFG_MAXARGS 16 /* max number of command args */
82#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
83
Wolfgang Denkf47b6612006-03-12 01:48:55 +010084#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
85#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
wdenk5b1d7132002-11-03 00:07:02 +000086
Wolfgang Denkf47b6612006-03-12 01:48:55 +010087#define CFG_RESET_ADDRESS 0x09900000
wdenk5b1d7132002-11-03 00:07:02 +000088
Wolfgang Denkf47b6612006-03-12 01:48:55 +010089#define CFG_LOAD_ADDR 0x400000 /* default load address */
90
91#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +000092
93#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
94
95/*
96 * Low Level Configuration Settings
97 * (address mappings, register initial values, etc.)
98 * You should know what you are doing if you make changes here.
99 */
100/*-----------------------------------------------------------------------
101 * Internal Memory Mapped Register
102 */
103#define CFG_IMMR 0xFA200000
104
105/*-----------------------------------------------------------------------
106 * Definitions for initial stack pointer and data area (in DPRAM)
107 */
108#define CFG_INIT_RAM_ADDR CFG_IMMR
109#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
110#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
111#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
112#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
113
114/*-----------------------------------------------------------------------
115 * Start addresses for the final memory configuration
116 * (Set up by the startup code)
117 * Please note that CFG_SDRAM_BASE _must_ start at 0
118 */
119#define CFG_SDRAM_BASE 0x00000000
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100120#define CFG_FLASH_BASE 0xFFC00000
121#define CFG_MONITOR_BASE TEXT_BASE
wdenk5b1d7132002-11-03 00:07:02 +0000122#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100123#ifdef CONFIG_BZIP2
124#define CFG_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000125#else
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100126#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
127#endif /* CONFIG_BZIP2 */
wdenk5b1d7132002-11-03 00:07:02 +0000128
129/*
130 * For booting Linux, the board info and command line data
131 * have to be in the first 8 MB of memory, since this is
132 * the maximum mapped by the Linux kernel during initialization.
133 */
134#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
135
136/*-----------------------------------------------------------------------
137 * FLASH organization
138 */
139#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
140#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
141
142#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
143#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
144
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100145#define CFG_DIRECT_FLASH_TFTP
146
wdenk5b1d7132002-11-03 00:07:02 +0000147#define CFG_ENV_IS_IN_FLASH 1
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100148#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
149#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
150
151#define CONFIG_ENV_OVERWRITE
wdenk5b1d7132002-11-03 00:07:02 +0000152
153/*-----------------------------------------------------------------------
154 * Cache Configuration
155 */
156#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
157#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
158#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
159#endif
160
161/*-----------------------------------------------------------------------
162 * SYPCR - System Protection Control 11-9
163 * SYPCR can only be written once after reset!
164 *-----------------------------------------------------------------------
165 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
166 */
167#if defined(CONFIG_WATCHDOG)
168#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
169 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
170#else
171#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
172#endif
173
174/*-----------------------------------------------------------------------
175 * SIUMCR - SIU Module Configuration 11-6
176 *-----------------------------------------------------------------------
177 * PCMCIA config., multi-function pin tri-state
178 */
179#define CFG_SIUMCR (SIUMCR_MLRC10)
180
181/*-----------------------------------------------------------------------
182 * TBSCR - Time Base Status and Control 11-26
183 *-----------------------------------------------------------------------
184 * Clear Reference Interrupt Status, Timebase freezing enabled
185 */
186#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
187
188/*-----------------------------------------------------------------------
189 * RTCSC - Real-Time Clock Status and Control Register 11-27
190 *-----------------------------------------------------------------------
191 */
192/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
193#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
194
195/*-----------------------------------------------------------------------
196 * PISCR - Periodic Interrupt Status and Control 11-31
197 *-----------------------------------------------------------------------
198 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
199 */
200#define CFG_PISCR (PISCR_PS | PISCR_PITF)
201
202/*-----------------------------------------------------------------------
203 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
204 *-----------------------------------------------------------------------
205 * Reset PLL lock status sticky bit, timer expired status bit and timer
206 * interrupt status bit
207 *
208 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
209 */
210/* up to 50 MHz we use a 1:1 clock */
211#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
212
213/*-----------------------------------------------------------------------
214 * SCCR - System Clock and reset Control Register 15-27
215 *-----------------------------------------------------------------------
216 * Set clock output, timebase and RTC source and divider,
217 * power management and some other internal clocks
218 */
219#define SCCR_MASK SCCR_EBDF00
220/* up to 50 MHz we use a 1:1 clock */
221#define CFG_SCCR (SCCR_COM11 | SCCR_TBS)
222
223/*-----------------------------------------------------------------------
224 * PCMCIA stuff
225 *-----------------------------------------------------------------------
226 *
227 */
228#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
229#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
230#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
231#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
232#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
233#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
234#define CFG_PCMCIA_IO_ADDR (0xEC000000)
235#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
236
237/*-----------------------------------------------------------------------
238 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
239 *-----------------------------------------------------------------------
240 */
241
242#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
243
244#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
245#undef CONFIG_IDE_LED /* LED for ide not supported */
246#undef CONFIG_IDE_RESET /* reset for ide not supported */
247
248#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
249#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
250
251#define CFG_ATA_IDE0_OFFSET 0x0000
252
253#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
254
255/* Offset for data I/O */
256#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
257
258/* Offset for normal register accesses */
259#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
260
261/* Offset for alternate registers */
262#define CFG_ATA_ALT_OFFSET 0x0100
263
264/*-----------------------------------------------------------------------
265 *
266 *-----------------------------------------------------------------------
267 *
268 */
269/*#define CFG_DER 0x2002000F*/
270#define CFG_DER 0
271
272/*
273 * Init Memory Controller:
274 *
275 * BR0 and OR0 (FLASH)
276 */
277
278#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
279#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
280
281/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
282#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
283
284#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
285#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
286
287/*
288 * BR1 and OR1 (SDRAM)
289 *
290 */
291#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
292#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
293
294/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
295#define CFG_OR_TIMING_SDRAM 0x00000E00
296
297#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
298#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
299
300/* RPXLITE mem setting */
301#define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
302#define CFG_OR3_PRELIM 0xFFFF8910
303#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
304#define CFG_OR4_PRELIM 0xFFFE0970
305
306/*
307 * Memory Periodic Timer Prescaler
308 */
309
310/* periodic timer for refresh */
311#define CFG_MAMR_PTA 58
312
313/*
314 * Refresh clock Prescalar
315 */
316#define CFG_MPTPR MPTPR_PTP_DIV8
317
318/*
319 * MAMR settings for SDRAM
320 */
321
322/* 10 column SDRAM */
323#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
324 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
325 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
326
327/*
328 * Internal Definitions
329 *
330 * Boot Flags
331 */
332#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
333#define BOOTFLAG_WARM 0x02 /* Software reboot */
334
335
336/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
337/* Configuration variable added by yooth. */
338/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
339
340/*
341 * BCSRx
342 *
343 * Board Status and Control Registers
344 *
345 */
346
347#define BCSR0 0xFA400000
348#define BCSR1 0xFA400001
349#define BCSR2 0xFA400002
350#define BCSR3 0xFA400003
351
352#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
353#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100354#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
355#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
wdenk5b1d7132002-11-03 00:07:02 +0000356#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
357#define BCSR0_COLTEST 0x20
358#define BCSR0_ETHLPBK 0x40
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100359#define BCSR0_ETHEN 0x80
wdenk5b1d7132002-11-03 00:07:02 +0000360
361#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
362#define BCSR1_PCVCTL6 0x02
363#define BCSR1_PCVCTL5 0x04
364#define BCSR1_PCVCTL4 0x08
365#define BCSR1_IPB5SEL 0x10
366
367#define BCSR2_ENPA5HDR 0x08 /* USB Control */
368#define BCSR2_ENUSBCLK 0x10
369#define BCSR2_USBPWREN 0x20
370#define BCSR2_USBSPD 0x40
371#define BCSR2_USBSUSP 0x80
372
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100373#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
374#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
wdenk5b1d7132002-11-03 00:07:02 +0000375#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
Wolfgang Denkf47b6612006-03-12 01:48:55 +0100376#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
377#define BCSR3_D27 0x10 /* Dip Switch settings */
378#define BCSR3_D26 0x20
379#define BCSR3_D25 0x40
380#define BCSR3_D24 0x80
wdenk5b1d7132002-11-03 00:07:02 +0000381
382#endif /* __CONFIG_H */