blob: a8af950b65d39004bde584dbcd487025f1dbffa6 [file] [log] [blame]
wdenkf832d8a2004-06-10 21:55:33 +00001/*
2 * See file CREDITS for list of people who contributed to this
3 * project.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/*
22 * Logic LH7A400-10 card engine
23 */
24
25#ifndef __LPD7A404_10_H
26#define __LPD7A404_10_H
27
28
29#define CONFIG_ARM920T 1 /* arm920t core */
30#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */
31#define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */
32
33/* The system clock PLL input frequency */
34#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */
35
36/* ticks per second */
37#define CFG_HZ (508469)
38
39/*-----------------------------------------------------------------------
40 * Stack sizes
41 *
42 * The stack sizes are set up in start.S using the settings below
43 */
44#define CONFIG_STACKSIZE (128*1024) /* regular stack */
45#ifdef CONFIG_USE_IRQ
46#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
47#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
48#endif
49
50/*-----------------------------------------------------------------------
51 * Physical Memory Map
52 */
53#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
54#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
55#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
56
57#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
58
59/*-----------------------------------------------------------------------
60 * FLASH and environment organization
61 */
62#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
63#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
64
65/* timeout values are in ticks */
66#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
67#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
68
69/*----------------------------------------------------------------------
70 * Using SMC91C111 LAN chip
71 *
72 * Default IO base of chip is 0x300, Card Engine has this address lines
73 * (LAN chip) tied to Vcc, so we just care about the chip select
74 */
75#define CONFIG_DRIVER_SMC91111
76#define CONFIG_SMC91111_BASE (0x70000000)
77#undef CONFIG_SMC_USE_32_BIT
78#define CONFIG_SMC_USE_IOFUNCS
79
80#endif /* __LPD7A404_10_H */