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wdenkc3c7f862004-06-09 14:47:54 +00001/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * Support for Interphase iSPAN Communications Controllers
6 * (453x and others). Tested on 4532.
7 *
8 * Derived from iSPAN 4539 port (iphase4539) by
9 * Wolfgang Grandegger <wg@denx.de>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
33#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050034#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkc3c7f862004-06-09 14:47:54 +000035
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
37
wdenkc3c7f862004-06-09 14:47:54 +000038/*-----------------------------------------------------------------------
39 * Select serial console configuration
40 *
41 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
42 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
43 * for SCC).
44 *
45 * If CONFIG_CONS_NONE is defined, then the serial console routines must be
46 * defined elsewhere (for example, on the cogent platform, there are serial
47 * ports on the motherboard which are used for the serial console - see
48 * cogent/cma101/serial.[ch]).
49 */
50#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
51#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
52#undef CONFIG_CONS_NONE /* Define if console on something else */
53#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
54
55/*-----------------------------------------------------------------------
56 * Select Ethernet configuration
57 *
58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
59 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
60 * for FCC).
61 *
62 * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
Jon Loeliger639221c2007-07-09 17:15:49 -050063 * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkc3c7f862004-06-09 14:47:54 +000064 */
65#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
66#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
67#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
68#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
69
70#ifdef CONFIG_ETHER_ON_FCC
71
72#if CONFIG_ETHER_INDEX == 3
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_PHY_ADDR 0
Mike Frysingerd4590da2011-10-17 05:38:58 +000075#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
76#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
wdenkc3c7f862004-06-09 14:47:54 +000077
78#endif /* CONFIG_ETHER_INDEX == 3 */
79
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_CPMFCR_RAMTYPE 0
81#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkc3c7f862004-06-09 14:47:54 +000082
83#define CONFIG_MII /* MII PHY management */
84#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
85/*
86 * GPIO pins used for bit-banged MII communications
87 */
88#define MDIO_PORT 3 /* Port D */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020089#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
90 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
91#define MDC_DECLARE MDIO_DECLARE
92
wdenkc3c7f862004-06-09 14:47:54 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
95#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
wdenkc3c7f862004-06-09 14:47:54 +000096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
98#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
99#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
wdenkc3c7f862004-06-09 14:47:54 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
102 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
wdenkc3c7f862004-06-09 14:47:54 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
105 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
wdenkc3c7f862004-06-09 14:47:54 +0000106
107#define MIIDELAY udelay(1)
108
109#endif /* CONFIG_ETHER_ON_FCC */
110
111#define CONFIG_8260_CLKIN 65536000 /* in Hz */
112#define CONFIG_BAUDRATE 38400
113
wdenkc3c7f862004-06-09 14:47:54 +0000114
Jon Loeliger348f2582007-07-08 13:46:18 -0500115/*
Jon Loeliger11799432007-07-10 09:02:57 -0500116 * BOOTP options
117 */
118#define CONFIG_BOOTP_BOOTFILESIZE
119#define CONFIG_BOOTP_BOOTPATH
120#define CONFIG_BOOTP_GATEWAY
121#define CONFIG_BOOTP_HOSTNAME
122
123
124/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500125 * Command line configuration.
126 */
127#include <config_cmd_default.h>
128
129#define CONFIG_CMD_ASKENV
130#define CONFIG_CMD_DHCP
131#define CONFIG_CMD_IMMAP
132#define CONFIG_CMD_MII
133#define CONFIG_CMD_PING
134#define CONFIG_CMD_REGINFO
135
wdenkc3c7f862004-06-09 14:47:54 +0000136
137#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
138#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
139#define CONFIG_BOOTARGS "root=/dev/ram rw"
140
141#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
142#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
143
144/*-----------------------------------------------------------------------
145 * Miscellaneous configurable options
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
148#define CONFIG_SYS_HUSH_PARSER
149#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
150#define CONFIG_SYS_LONGHELP /* #undef to save memory */
151#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
152#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
153#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
154#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc3c7f862004-06-09 14:47:54 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
157#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
wdenkc3c7f862004-06-09 14:47:54 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
wdenkc3c7f862004-06-09 14:47:54 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
wdenkc3c7f862004-06-09 14:47:54 +0000162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkc3c7f862004-06-09 14:47:54 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_RESET_ADDRESS 0x09900000
wdenkc3c7f862004-06-09 14:47:54 +0000166
167#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
168
169/*-----------------------------------------------------------------------
170 * For booting Linux, the board info and command line data
171 * have to be in the first 8 MB of memory, since this is
172 * the maximum mapped by the Linux kernel during initialization.
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc3c7f862004-06-09 14:47:54 +0000175
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200176#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenkc3c7f862004-06-09 14:47:54 +0000178#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
wdenkc3c7f862004-06-09 14:47:54 +0000180#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
wdenkc3c7f862004-06-09 14:47:54 +0000182#endif /* CONFIG_BZIP2 */
183
184/*-----------------------------------------------------------------------
185 * FLASH organization
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_BASE 0xFE000000
188#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200189#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
191#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
wdenkc3c7f862004-06-09 14:47:54 +0000192
193/* Environment is in flash, there is little space left in Serial EEPROM */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200194#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200195#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
196#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200198#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkc3c7f862004-06-09 14:47:54 +0000200
201/*-----------------------------------------------------------------------
202 * Hard Reset Configuration Words
203 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenkc3c7f862004-06-09 14:47:54 +0000205 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenkc3c7f862004-06-09 14:47:54 +0000207 */
208/* 0x1686B245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
wdenkc3c7f862004-06-09 14:47:54 +0000210 HRCW_L2CPC10 | HRCW_ISB110 |\
211 HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
212 HRCW_CS10PC01 | HRCW_MODCK_H0101 \
213 )
214/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_HRCW_SLAVE1 0
216#define CONFIG_SYS_HRCW_SLAVE2 0
217#define CONFIG_SYS_HRCW_SLAVE3 0
218#define CONFIG_SYS_HRCW_SLAVE4 0
219#define CONFIG_SYS_HRCW_SLAVE5 0
220#define CONFIG_SYS_HRCW_SLAVE6 0
221#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkc3c7f862004-06-09 14:47:54 +0000222
223/*-----------------------------------------------------------------------
224 * Internal Memory Mapped Register
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_IMMR 0xF0F00000
227#ifdef CONFIG_SYS_REV_B
228#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
229#endif /* CONFIG_SYS_REV_B */
wdenkc3c7f862004-06-09 14:47:54 +0000230/*-----------------------------------------------------------------------
231 * Definitions for initial stack pointer and data area (in DPRAM)
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200234#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200235#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc3c7f862004-06-09 14:47:54 +0000237
238/*-----------------------------------------------------------------------
wdenkc3c7f862004-06-09 14:47:54 +0000239 * Cache Configuration
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkc3c7f862004-06-09 14:47:54 +0000242
243/*-----------------------------------------------------------------------
244 * HIDx - Hardware Implementation-dependent Registers 2-11
245 *-----------------------------------------------------------------------
246 * HID0 also contains cache control.
247 *
248 * HID1 has only read-only information - nothing to set.
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenkc3c7f862004-06-09 14:47:54 +0000251 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
253#define CONFIG_SYS_HID2 0
wdenkc3c7f862004-06-09 14:47:54 +0000254
255/*-----------------------------------------------------------------------
256 * RMR - Reset Mode Register 5-5
257 *-----------------------------------------------------------------------
258 * turn on Checkstop Reset Enable
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_RMR RMR_CSRE
wdenkc3c7f862004-06-09 14:47:54 +0000261
262/*-----------------------------------------------------------------------
263 * BCR - Bus Configuration 4-25
264 *-----------------------------------------------------------------------
265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BCR 0xA01C0000
wdenkc3c7f862004-06-09 14:47:54 +0000267
268/*-----------------------------------------------------------------------
269 * SIUMCR - SIU Module Configuration 4-31
270 *-----------------------------------------------------------------------
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
wdenkc3c7f862004-06-09 14:47:54 +0000273
274/*-----------------------------------------------------------------------
275 * SYPCR - System Protection Control 4-35
276 * SYPCR can only be written once after reset!
277 *-----------------------------------------------------------------------
278 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
279 */
280#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenkc3c7f862004-06-09 14:47:54 +0000282 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
283#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenkc3c7f862004-06-09 14:47:54 +0000285 SYPCR_SWRI|SYPCR_SWP)
286#endif /* CONFIG_WATCHDOG */
287
288/*-----------------------------------------------------------------------
289 * TMCNTSC - Time Counter Status and Control 4-40
290 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
291 * and enable Time Counter
292 *-----------------------------------------------------------------------
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenkc3c7f862004-06-09 14:47:54 +0000295
296/*-----------------------------------------------------------------------
297 * PISCR - Periodic Interrupt Status and Control 4-42
298 *-----------------------------------------------------------------------
299 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
300 * Periodic timer
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenkc3c7f862004-06-09 14:47:54 +0000303
304/*-----------------------------------------------------------------------
305 * SCCR - System Clock Control 9-8
306 *-----------------------------------------------------------------------
307 * Ensure DFBRG is Divide by 16
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenkc3c7f862004-06-09 14:47:54 +0000310
311/*-----------------------------------------------------------------------
312 * RCCR - RISC Controller Configuration 13-7
313 *-----------------------------------------------------------------------
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_RCCR 0
wdenkc3c7f862004-06-09 14:47:54 +0000316
317/*-----------------------------------------------------------------------
318 * Init Memory Controller:
319 *
320 * Bank Bus Machine PortSize Device
321 * ---- --- ------- ----------------------------- ------
322 * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
323 * 1 60x SDRAM 64 bit SDRAM
324 * 2 Local SDRAM 32 bit SDRAM
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
wdenkc3c7f862004-06-09 14:47:54 +0000327 controller, rely on initialisation
328 performed by the Interphase boot firmware.
329 */
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_OR0_PRELIM 0xFE000882
332#ifdef CONFIG_SYS_REV_B
333#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
wdenkc3c7f862004-06-09 14:47:54 +0000334#else /* Rev. D */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
336#endif /* CONFIG_SYS_REV_B */
wdenkc3c7f862004-06-09 14:47:54 +0000337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_MPTPR 0x7F00
wdenkc3c7f862004-06-09 14:47:54 +0000339
340/* Please note that 60x SDRAM MUST start at 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_SDRAM_BASE 0x00000000
342#define CONFIG_SYS_60x_BR 0x00000041
343#define CONFIG_SYS_60x_OR 0xF0002CD0
344#define CONFIG_SYS_PSDMR 0x0049929A
345#define CONFIG_SYS_PSRT 0x07
wdenkc3c7f862004-06-09 14:47:54 +0000346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
348#define CONFIG_SYS_LOC_BR 0x00001861
349#define CONFIG_SYS_LOC_OR 0xFF803280
350#define CONFIG_SYS_LSDMR 0x8285A552
351#define CONFIG_SYS_LSRT 0x07
wdenkc3c7f862004-06-09 14:47:54 +0000352
353#endif /* __CONFIG_H */