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Daniel Hellstromab68f922008-03-28 10:20:43 +01001/* Configuration header file for LEON2 GRSIM.
2 *
3 * (C) Copyright 2003-2005
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007
7 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H__
29#define __CONFIG_H__
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 *
35 * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
36 *
37 * TSIM command
38 * tsim-leon -sdram 0 -ram 32000 -rom 8192 -mmu
39 *
40 */
41
42#define CONFIG_LEON2 /* This is an LEON2 CPU */
43#define CONFIG_LEON 1 /* This is an LEON CPU */
44#define CONFIG_GRSIM 0 /* ... not running on GRSIM */
45#define CONFIG_TSIM 1 /* ... running on TSIM */
46
47/* CPU / AMBA BUS configuration */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */
Daniel Hellstromab68f922008-03-28 10:20:43 +010049
50/* Number of SPARC register windows */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_SPARC_NWINDOWS 8
Daniel Hellstromab68f922008-03-28 10:20:43 +010052
53/*
54 * Serial console configuration
55 */
56#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstromab68f922008-03-28 10:20:43 +010058
59/* Partitions */
60#define CONFIG_DOS_PARTITION
61#define CONFIG_MAC_PARTITION
62#define CONFIG_ISO_PARTITION
63
64/*
65 * Supported commands
66 */
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020067#define CONFIG_CMD_BDI /* bdinfo */
68#define CONFIG_CMD_CONSOLE /* coninfo */
Daniel Hellstromab68f922008-03-28 10:20:43 +010069#define CONFIG_CMD_DIAG
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020070#define CONFIG_CMD_ECHO /* echo arguments */
71#define CONFIG_CMD_FPGA /* FPGA configuration Support */
Daniel Hellstromab68f922008-03-28 10:20:43 +010072#define CONFIG_CMD_IRQ
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020073#define CONFIG_CMD_ITEST /* Integer (and string) test */
74#define CONFIG_CMD_LOADB /* loadb */
75#define CONFIG_CMD_LOADS /* loads */
Daniel Hellstromab68f922008-03-28 10:20:43 +010076#define CONFIG_CMD_MISC /* Misc functions like sleep etc */
77#define CONFIG_CMD_REGINFO
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020078#define CONFIG_CMD_RUN /* run command in env variable */
79#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
80#define CONFIG_CMD_SOURCE /* "source" command support */
81#define CONFIG_CMD_XIMG /* Load part of Multi Image */
Daniel Hellstromab68f922008-03-28 10:20:43 +010082
83/*
84 * Autobooting
85 */
86#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
87
88#define CONFIG_PREBOOT "echo;" \
89 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
90 "echo"
91
92#undef CONFIG_BOOTARGS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093/*#define CONFIG_SYS_HUSH_PARSER 0*/
94#ifdef CONFIG_SYS_HUSH_PARSER
95#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Daniel Hellstromab68f922008-03-28 10:20:43 +010096#endif
97
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "nfsargs=setenv bootargs root=/dev/nfs rw " \
101 "nfsroot=${serverip}:${rootpath}\0" \
102 "ramargs=setenv bootargs root=/dev/ram rw\0" \
103 "addip=setenv bootargs ${bootargs} " \
104 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
105 ":${hostname}:${netdev}:off panic=1\0" \
106 "flash_nfs=run nfsargs addip;" \
107 "bootm ${kernel_addr}\0" \
108 "flash_self=run ramargs addip;" \
109 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
110 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
111 "rootpath=/export/roofs\0" \
112 "scratch=40000000\0" \
Mike Frysinger3a2b9f22011-10-12 19:47:51 +0000113 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstromab68f922008-03-28 10:20:43 +0100114 "ethaddr=00:00:7A:CC:00:12\0" \
115 "bootargs=console=ttyS0,38400" \
116 ""
117#define CONFIG_NETMASK 255.255.255.0
118#define CONFIG_GATEWAYIP 192.168.0.1
119#define CONFIG_SERVERIP 192.168.0.81
120#define CONFIG_IPADDR 192.168.0.80
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000121#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstromab68f922008-03-28 10:20:43 +0100122#define CONFIG_HOSTNAME grxc3s1500
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000123#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstromab68f922008-03-28 10:20:43 +0100124
125#define CONFIG_BOOTCOMMAND "run flash_self"
126
127/* Memory MAP
128 *
129 * Flash:
130 * |--------------------------------|
131 * | 0x00000000 Text & Data & BSS | *
132 * | for Monitor | *
133 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
134 * | UNUSED / Growth | * 256kb
135 * |--------------------------------|
136 * | 0x00050000 Base custom area | *
137 * | kernel / FS | *
138 * | | * Rest of Flash
139 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
140 * | END-0x00008000 Environment | * 32kb
141 * |--------------------------------|
142 *
143 *
144 *
145 * Main Memory:
146 * |--------------------------------|
147 * | UNUSED / scratch area |
148 * | |
149 * | |
150 * | |
151 * | |
152 * |--------------------------------|
153 * | Monitor .Text / .DATA / .BSS | * 256kb
154 * | Relocated! | *
155 * |--------------------------------|
156 * | Monitor Malloc | * 128kb (contains relocated environment)
157 * |--------------------------------|
158 * | Monitor/kernel STACK | * 64kb
159 * |--------------------------------|
160 * | Page Table for MMU systems | * 2k
161 * |--------------------------------|
162 * | PROM Code accessed from Linux | * 6kb-128b
163 * |--------------------------------|
164 * | Global data (avail from kernel)| * 128b
165 * |--------------------------------|
166 *
167 */
168
169/*
170 * Flash configuration (8,16 or 32 MB)
171 * TEXT base always at 0xFFF00000
172 * ENV_ADDR always at 0xFFF40000
173 * FLASH_BASE at 0xFC000000 for 64 MB
174 * 0xFE000000 for 32 MB
175 * 0xFF000000 for 16 MB
176 * 0xFF800000 for 8 MB
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_NO_FLASH 1
179#define CONFIG_SYS_FLASH_BASE 0x00000000
180#define CONFIG_SYS_FLASH_SIZE 0x00800000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200181#define CONFIG_ENV_SIZE 0x8000
Daniel Hellstromab68f922008-03-28 10:20:43 +0100182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100184
185#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
187#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
190#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
191#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
192#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100193
194#ifdef ENABLE_FLASH_SUPPORT
195/* For use with grsim FLASH emulation extension */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100197
198#undef CONFIG_FLASH_8BIT /* Flash is 32-bit */
199
200/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200202#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_CFI
Daniel Hellstromab68f922008-03-28 10:20:43 +0100204#endif
205
206/*
207 * Environment settings
208 */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200209#define CONFIG_ENV_IS_NOWHERE 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200210/*#define CONFIG_ENV_IS_IN_FLASH*/
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200211/*#define CONFIG_ENV_SIZE 0x8000*/
212#define CONFIG_ENV_SECT_SIZE 0x40000
Daniel Hellstromab68f922008-03-28 10:20:43 +0100213#define CONFIG_ENV_OVERWRITE 1
214
215/*
216 * Memory map
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_SDRAM_BASE 0x40000000
219#define CONFIG_SYS_SDRAM_SIZE 0x00800000
220#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100221
222/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#undef CONFIG_SYS_SRAM_BASE
224#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstromab68f922008-03-28 10:20:43 +0100225
226
227/* Always Run U-Boot from SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
229#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
230#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstromab68f922008-03-28 10:20:43 +0100231
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100233
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200234#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
238#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100239
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200240#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
242# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstromab68f922008-03-28 10:20:43 +0100243#endif
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
246#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
247#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
250#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100251
252/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
254#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100255
256/* make un relocated address from relocated address */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200257#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstromab68f922008-03-28 10:20:43 +0100258
259/*
260 * Ethernet configuration
261 */
262/*#define CONFIG_GRETH 1*/
Daniel Hellstromab68f922008-03-28 10:20:43 +0100263
264/* Default HARDWARE address */
265#define GRETH_HWADDR_0 0x00
266#define GRETH_HWADDR_1 0x00
267#define GRETH_HWADDR_2 0x7A
268#define GRETH_HWADDR_3 0xcc
269#define GRETH_HWADDR_4 0x00
270#define GRETH_HWADDR_5 0x12
271
272#define CONFIG_ETHADDR 00:00:7a:cc:00:12
273
274/*
275 * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
276 */
277/* #define CONFIG_GRETH_10MBIT 1 */
278#define CONFIG_PHY_ADDR 0x00
279
280/*
281 * Miscellaneous configurable options
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_LONGHELP /* undef to save memory */
284#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100285#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100287#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100289#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
291#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
292#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
295#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Daniel Hellstromab68f922008-03-28 10:20:43 +0100300
301/***** Gaisler GRLIB IP-Cores Config ********/
302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_GRLIB_SDRAM 0
304#define CONFIG_SYS_GRLIB_MEMCFG1 (0x000000ff | (1<<11))
Daniel Hellstromab68f922008-03-28 10:20:43 +0100305#if CONFIG_GRSIM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_GRLIB_MEMCFG2 0x82206000
Daniel Hellstromab68f922008-03-28 10:20:43 +0100307#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_GRLIB_MEMCFG2 0x00001820
Daniel Hellstromab68f922008-03-28 10:20:43 +0100309#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_GRLIB_MEMCFG3 0x00136000
Daniel Hellstromab68f922008-03-28 10:20:43 +0100311
312/*** LEON2 UART 1 ***/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_LEON2_UART1_SCALER \
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700314 ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
315
Daniel Hellstromab68f922008-03-28 10:20:43 +0100316/* UART1 Define to 1 or 0 */
317#define LEON2_UART1_LOOPBACK_ENABLE 0
318#define LEON2_UART1_FLOWCTRL_ENABLE 0
319#define LEON2_UART1_PARITY_ENABLE 0
320#define LEON2_UART1_ODDPAR_ENABLE 0
321
322/*** LEON2 UART 2 ***/
323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_LEON2_UART2_SCALER \
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -0700325 ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
Daniel Hellstromab68f922008-03-28 10:20:43 +0100326
327/* UART2 Define to 1 or 0 */
328#define LEON2_UART2_LOOPBACK_ENABLE 0
329#define LEON2_UART2_FLOWCTRL_ENABLE 0
330#define LEON2_UART2_PARITY_ENABLE 0
331#define LEON2_UART2_ODDPAR_ENABLE 0
332
333#define LEON_CONSOLE_UART1 1
334#define LEON_CONSOLE_UART2 2
335
336/* Use UART2 as console */
337#define LEON2_CONSOLE_SELECT LEON_CONSOLE_UART1
338
339/* LEON2 I/O Port */
340/*#define LEON2_IO_PORT_DIR 0x0000aa00*/
341
342/* default kernel command line */
343#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
344
345#define CONFIG_IDENT_STRING "Gaisler GRSIM LEON2"
346
347#endif /* __CONFIG_H */