blob: c0ae9472424541d20343e2ea2185d8202dafe8f1 [file] [log] [blame]
wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * (C) Copyright 2004
6 * ARM Ltd.
7 * Philippe Robin, <philippe.robin@arm.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Andreas Engel48d01922008-09-08 14:30:53 +020028/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
wdenk3d3befa2004-03-14 15:06:13 +000029
30#include <common.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040031#include <watchdog.h>
Matt Waddel249d5212010-10-07 15:48:46 -060032#include <asm/io.h>
Andreas Engel20c92262008-09-08 10:17:31 +020033#include "serial_pl01x.h"
wdenk3d3befa2004-03-14 15:06:13 +000034
Andreas Engel20c92262008-09-08 10:17:31 +020035/*
36 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
37 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
38 * Versatile PB has four UARTs.
39 */
wdenk3d3befa2004-03-14 15:06:13 +000040#define CONSOLE_PORT CONFIG_CONS_INDEX
wdenk6705d812004-08-02 23:22:59 +000041static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
42#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000043
Andreas Engel20c92262008-09-08 10:17:31 +020044static void pl01x_putc (int portnum, char c);
45static int pl01x_getc (int portnum);
46static int pl01x_tstc (int portnum);
Matt Waddel249d5212010-10-07 15:48:46 -060047unsigned int baudrate = CONFIG_BAUDRATE;
48DECLARE_GLOBAL_DATA_PTR;
wdenk3d3befa2004-03-14 15:06:13 +000049
Andreas Engel48d01922008-09-08 14:30:53 +020050#ifdef CONFIG_PL010_SERIAL
wdenk3d3befa2004-03-14 15:06:13 +000051
52int serial_init (void)
53{
wdenk42dfe7a2004-03-14 22:25:36 +000054 unsigned int divisor;
wdenk3d3befa2004-03-14 15:06:13 +000055
Matt Waddel249d5212010-10-07 15:48:46 -060056 /* First, disable everything */
57 writel(0x0, port[CONSOLE_PORT] + UART_PL010_CR);
wdenk3d3befa2004-03-14 15:06:13 +000058
Matt Waddel249d5212010-10-07 15:48:46 -060059 /* Set baud rate */
60 switch (baudrate) {
wdenk42dfe7a2004-03-14 22:25:36 +000061 case 9600:
62 divisor = UART_PL010_BAUD_9600;
63 break;
wdenk3d3befa2004-03-14 15:06:13 +000064
wdenk42dfe7a2004-03-14 22:25:36 +000065 case 19200:
66 divisor = UART_PL010_BAUD_9600;
67 break;
wdenk3d3befa2004-03-14 15:06:13 +000068
wdenk42dfe7a2004-03-14 22:25:36 +000069 case 38400:
70 divisor = UART_PL010_BAUD_38400;
71 break;
wdenk3d3befa2004-03-14 15:06:13 +000072
wdenk42dfe7a2004-03-14 22:25:36 +000073 case 57600:
74 divisor = UART_PL010_BAUD_57600;
75 break;
wdenk3d3befa2004-03-14 15:06:13 +000076
wdenk42dfe7a2004-03-14 22:25:36 +000077 case 115200:
78 divisor = UART_PL010_BAUD_115200;
79 break;
wdenk3d3befa2004-03-14 15:06:13 +000080
wdenk42dfe7a2004-03-14 22:25:36 +000081 default:
82 divisor = UART_PL010_BAUD_38400;
83 }
wdenk3d3befa2004-03-14 15:06:13 +000084
Matt Waddel249d5212010-10-07 15:48:46 -060085 writel(((divisor & 0xf00) >> 8), port[CONSOLE_PORT] + UART_PL010_LCRM);
86 writel((divisor & 0xff), port[CONSOLE_PORT] + UART_PL010_LCRL);
wdenk3d3befa2004-03-14 15:06:13 +000087
Matt Waddel249d5212010-10-07 15:48:46 -060088 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
89 writel((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN),
90 port[CONSOLE_PORT] + UART_PL010_LCRH);
wdenk3d3befa2004-03-14 15:06:13 +000091
Matt Waddel249d5212010-10-07 15:48:46 -060092 /* Finally, enable the UART */
93 writel((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR);
wdenk42dfe7a2004-03-14 22:25:36 +000094
Andreas Engel20c92262008-09-08 10:17:31 +020095 return 0;
wdenk3d3befa2004-03-14 15:06:13 +000096}
97
Andreas Engel48d01922008-09-08 14:30:53 +020098#endif /* CONFIG_PL010_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +020099
Andreas Engel48d01922008-09-08 14:30:53 +0200100#ifdef CONFIG_PL011_SERIAL
Andreas Engel20c92262008-09-08 10:17:31 +0200101
102int serial_init (void)
103{
104 unsigned int temp;
105 unsigned int divider;
106 unsigned int remainder;
107 unsigned int fraction;
108
Matt Waddel249d5212010-10-07 15:48:46 -0600109 /* First, disable everything */
110 writel(0x0, port[CONSOLE_PORT] + UART_PL011_CR);
Andreas Engel20c92262008-09-08 10:17:31 +0200111
112 /*
Matt Waddel249d5212010-10-07 15:48:46 -0600113 * Set baud rate
114 *
115 * IBRD = UART_CLK / (16 * BAUD_RATE)
116 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
Andreas Engel20c92262008-09-08 10:17:31 +0200117 */
Matt Waddel249d5212010-10-07 15:48:46 -0600118 temp = 16 * baudrate;
Andreas Engel20c92262008-09-08 10:17:31 +0200119 divider = CONFIG_PL011_CLOCK / temp;
120 remainder = CONFIG_PL011_CLOCK % temp;
Matt Waddel249d5212010-10-07 15:48:46 -0600121 temp = (8 * remainder) / baudrate;
Andreas Engel20c92262008-09-08 10:17:31 +0200122 fraction = (temp >> 1) + (temp & 1);
123
Matt Waddel249d5212010-10-07 15:48:46 -0600124 writel(divider, port[CONSOLE_PORT] + UART_PL011_IBRD);
125 writel(fraction, port[CONSOLE_PORT] + UART_PL011_FBRD);
Andreas Engel20c92262008-09-08 10:17:31 +0200126
Matt Waddel249d5212010-10-07 15:48:46 -0600127 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
128 writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN),
129 port[CONSOLE_PORT] + UART_PL011_LCRH);
Andreas Engel20c92262008-09-08 10:17:31 +0200130
Matt Waddel249d5212010-10-07 15:48:46 -0600131 /* Finally, enable the UART */
132 writel((UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE),
133 port[CONSOLE_PORT] + UART_PL011_CR);
Andreas Engel20c92262008-09-08 10:17:31 +0200134
135 return 0;
136}
137
Andreas Engel48d01922008-09-08 14:30:53 +0200138#endif /* CONFIG_PL011_SERIAL */
Andreas Engel20c92262008-09-08 10:17:31 +0200139
wdenk42dfe7a2004-03-14 22:25:36 +0000140void serial_putc (const char c)
wdenk3d3befa2004-03-14 15:06:13 +0000141{
142 if (c == '\n')
Andreas Engel20c92262008-09-08 10:17:31 +0200143 pl01x_putc (CONSOLE_PORT, '\r');
wdenk3d3befa2004-03-14 15:06:13 +0000144
Andreas Engel20c92262008-09-08 10:17:31 +0200145 pl01x_putc (CONSOLE_PORT, c);
wdenk3d3befa2004-03-14 15:06:13 +0000146}
147
wdenk42dfe7a2004-03-14 22:25:36 +0000148void serial_puts (const char *s)
wdenk3d3befa2004-03-14 15:06:13 +0000149{
150 while (*s) {
151 serial_putc (*s++);
152 }
153}
154
wdenk42dfe7a2004-03-14 22:25:36 +0000155int serial_getc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000156{
Andreas Engel20c92262008-09-08 10:17:31 +0200157 return pl01x_getc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000158}
159
wdenk42dfe7a2004-03-14 22:25:36 +0000160int serial_tstc (void)
wdenk3d3befa2004-03-14 15:06:13 +0000161{
Andreas Engel20c92262008-09-08 10:17:31 +0200162 return pl01x_tstc (CONSOLE_PORT);
wdenk3d3befa2004-03-14 15:06:13 +0000163}
164
wdenk42dfe7a2004-03-14 22:25:36 +0000165void serial_setbrg (void)
wdenk3d3befa2004-03-14 15:06:13 +0000166{
Matt Waddel249d5212010-10-07 15:48:46 -0600167 baudrate = gd->baudrate;
168 serial_init();
wdenk3d3befa2004-03-14 15:06:13 +0000169}
170
Andreas Engel20c92262008-09-08 10:17:31 +0200171static void pl01x_putc (int portnum, char c)
wdenk3d3befa2004-03-14 15:06:13 +0000172{
wdenk42dfe7a2004-03-14 22:25:36 +0000173 /* Wait until there is space in the FIFO */
Matt Waddel249d5212010-10-07 15:48:46 -0600174 while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
Stuart Wood8b616ed2008-06-02 16:42:19 -0400175 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000176
177 /* Send the character */
Matt Waddel249d5212010-10-07 15:48:46 -0600178 writel(c, port[portnum] + UART_PL01x_DR);
wdenk3d3befa2004-03-14 15:06:13 +0000179}
180
Andreas Engel20c92262008-09-08 10:17:31 +0200181static int pl01x_getc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000182{
wdenk42dfe7a2004-03-14 22:25:36 +0000183 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +0000184
wdenk42dfe7a2004-03-14 22:25:36 +0000185 /* Wait until there is data in the FIFO */
Matt Waddel249d5212010-10-07 15:48:46 -0600186 while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
Stuart Wood8b616ed2008-06-02 16:42:19 -0400187 WATCHDOG_RESET();
wdenk42dfe7a2004-03-14 22:25:36 +0000188
Matt Waddel249d5212010-10-07 15:48:46 -0600189 data = readl(port[portnum] + UART_PL01x_DR);
wdenk42dfe7a2004-03-14 22:25:36 +0000190
191 /* Check for an error flag */
192 if (data & 0xFFFFFF00) {
193 /* Clear the error */
Matt Waddel249d5212010-10-07 15:48:46 -0600194 writel(0xFFFFFFFF, port[portnum] + UART_PL01x_ECR);
wdenk42dfe7a2004-03-14 22:25:36 +0000195 return -1;
196 }
197
198 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +0000199}
200
Andreas Engel20c92262008-09-08 10:17:31 +0200201static int pl01x_tstc (int portnum)
wdenk3d3befa2004-03-14 15:06:13 +0000202{
Stuart Wood8b616ed2008-06-02 16:42:19 -0400203 WATCHDOG_RESET();
Matt Waddel249d5212010-10-07 15:48:46 -0600204 return !(readl(port[portnum] + UART_PL01x_FR) &
wdenk42dfe7a2004-03-14 22:25:36 +0000205 UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +0000206}