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dzu@denx.de6ca24c62006-04-21 18:30:47 +02001/*
2 * -- Version 1.1 --
3 *
4 * (C) Copyright 2003-2005
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2005
8 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
9 *
10 * (C) Copyright 2005
11 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
12 *
13 * History:
14 * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/*
39 * High Level Configuration Options
40 */
41#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
42#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
43#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
44
Wolfgang Denk610cf362006-05-03 01:24:04 +020045#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
46#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
47#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020048#define CONFIG_BC3450_USB 1 /* + USB support */
49# define CONFIG_FAT 1 /* + FAT support */
50# define CONFIG_EXT2 1 /* + EXT2 support */
51#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
52#undef CONFIG_BC3450_CAN /* + CAN transceiver */
53#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
Wolfgang Denk610cf362006-05-03 01:24:04 +020054#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
55#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020056#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
57#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
58
Wolfgang Denk2ae18242010-10-06 09:05:45 +020059/*
60 * Valid values for CONFIG_SYS_TEXT_BASE are:
61 * 0xFC000000 boot low (standard configuration with room for
62 * max 64 MByte Flash ROM)
63 * 0x00100000 boot from RAM (for testing only)
64 */
65#ifndef CONFIG_SYS_TEXT_BASE
66#define CONFIG_SYS_TEXT_BASE 0xFC000000
67#endif
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020070
Becky Bruce31d82672008-05-08 19:02:12 -050071#define CONFIG_HIGH_BATS 1 /* High BATs supported */
72
dzu@denx.de6ca24c62006-04-21 18:30:47 +020073/*
74 * Serial console configuration
75 */
76#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
77#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
dzu@denx.de6ca24c62006-04-21 18:30:47 +020079
80/*
81 * AT-PS/2 Multiplexer
82 */
83#ifdef CONFIG_BC3450_PS2
84# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
85# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
86# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020088# define CONFIG_BOARD_EARLY_INIT_R
89#endif /* CONFIG_BC3450_PS2 */
90
91/*
92 * PCI Mapping:
93 * 0x40000000 - 0x4fffffff - PCI Memory
94 * 0x50000000 - 0x50ffffff - PCI IO Space
95 */
96# define CONFIG_PCI 1
97# define CONFIG_PCI_PNP 1
Wolfgang Denk610cf362006-05-03 01:24:04 +020098/* #define CONFIG_PCI_SCAN_SHOW 1 */
TsiChung Liewf33fca22008-03-30 01:19:06 -050099#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200100
101#define CONFIG_PCI_MEM_BUS 0x40000000
102#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
103#define CONFIG_PCI_MEM_SIZE 0x10000000
104
105#define CONFIG_PCI_IO_BUS 0x50000000
106#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
107#define CONFIG_PCI_IO_SIZE 0x01000000
108
109#define CONFIG_NET_MULTI 1
110/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200112#define CONFIG_NS8382X 1
113
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200114/*
115 * Video console
116 */
117# define CONFIG_VIDEO
118# define CONFIG_VIDEO_SM501
119# define CONFIG_VIDEO_SM501_32BPP
120# define CONFIG_CFB_CONSOLE
121# define CONFIG_VIDEO_LOGO
122# define CONFIG_VGA_AS_SINGLE_DEVICE
123# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
124# define CONFIG_VIDEO_SW_CURSOR
125# define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126# define CONFIG_SYS_CONSOLE_IS_IN_ENV
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200127
Wolfgang Denk610cf362006-05-03 01:24:04 +0200128/*
129 * Partitions
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200130 */
131#define CONFIG_MAC_PARTITION
132#define CONFIG_DOS_PARTITION
133#define CONFIG_ISO_PARTITION
134
Wolfgang Denk610cf362006-05-03 01:24:04 +0200135/*
136 * USB
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200137 */
138#ifdef CONFIG_BC3450_USB
139# define CONFIG_USB_OHCI
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200140# define CONFIG_USB_STORAGE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200141#endif /* CONFIG_BC3450_USB */
142
Wolfgang Denk610cf362006-05-03 01:24:04 +0200143/*
144 * POST support
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
147 CONFIG_SYS_POST_CPU | \
148 CONFIG_SYS_POST_I2C)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200149
150#ifdef CONFIG_POST
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200151/* preserve space for the post_word at end of on-chip SRAM */
152# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200153#endif /* CONFIG_POST */
154
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500155
Wolfgang Denk610cf362006-05-03 01:24:04 +0200156/*
Jon Loeliger11799432007-07-10 09:02:57 -0500157 * BOOTP options
158 */
159#define CONFIG_BOOTP_BOOTFILESIZE
160#define CONFIG_BOOTP_BOOTPATH
161#define CONFIG_BOOTP_GATEWAY
162#define CONFIG_BOOTP_HOSTNAME
163
164
165/*
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500166 * Command line configuration.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200167 */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500168#include <config_cmd_default.h>
169
170#define CONFIG_CMD_ASKENV
171#define CONFIG_CMD_DATE
172#define CONFIG_CMD_DHCP
173#define CONFIG_CMD_ECHO
174#define CONFIG_CMD_EEPROM
175#define CONFIG_CMD_I2C
176#define CONFIG_CMD_JFFS2
177#define CONFIG_CMD_MII
178#define CONFIG_CMD_NFS
179#define CONFIG_CMD_PING
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500180#define CONFIG_CMD_REGINFO
181#define CONFIG_CMD_SNTP
182#define CONFIG_CMD_BSP
183
184#ifdef CONFIG_VIDEO
185 #define CONFIG_CMD_BMP
186#endif
187
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200188#ifdef CONFIG_BC3450_IDE
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500189 #define CONFIG_CMD_IDE
190#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200191
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500192#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
193 #ifdef CONFIG_FAT
194 #define CONFIG_CMD_FAT
195 #endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200196
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500197 #ifdef CONFIG_EXT2
198 #define CONFIG_CMD_EXT2
199 #endif
200#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200201
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500202#ifdef CONFIG_BC3450_USB
203 #define CONFIG_CMD_USB
204#endif
Wolfgang Denk5728be32007-08-06 01:01:49 +0200205
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500206#ifdef CONFIG_PCI
207 #define CONFIG_CMD_PCI
208#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200209
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500210#ifdef CONFIG_POST
211 #define CONFIG_CMD_DIAG
212#endif
213
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200214
Wolfgang Denk610cf362006-05-03 01:24:04 +0200215#define CONFIG_TIMESTAMP /* display image timestamps */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200216
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200217#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218# define CONFIG_SYS_LOWBOOT 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200219#endif
220
221/*
222 * Autobooting
223 */
224#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
225#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
226
227#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100228 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200229 "echo;"
230
231#undef CONFIG_BOOTARGS
232
233#define CONFIG_EXTRA_ENV_SETTINGS \
234 "netdev=eth0\0" \
235 "ipaddr=192.168.1.10\0" \
236 "serverip=192.168.1.3\0" \
237 "netmask=255.255.255.0\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200238 "hostname=bc3450\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200239 "rootpath=/opt/eldk/ppc_6xx\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200240 "kernel_addr=fc0a0000\0" \
241 "ramdisk_addr=fc1c0000\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200242 "ramargs=setenv bootargs root=/dev/ram rw\0" \
243 "nfsargs=setenv bootargs root=/dev/nfs rw " \
244 "nfsroot=$(serverip):$(rootpath)\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200245 "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200246 "addip=setenv bootargs $(bootargs) " \
247 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
248 ":$(hostname):$(netdev):off panic=1\0" \
249 "addcons=setenv bootargs $(bootargs) " \
250 "console=ttyS0,$(baudrate) console=tty0\0" \
251 "flash_self=run ramargs addip addcons;" \
252 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
253 "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
254 "net_nfs=tftp 200000 $(bootfile); " \
255 "run nfsargs addip addcons; bootm\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200256 "ide_nfs=run nfsargs addip addcons; " \
257 "disk 200000 0:1; bootm\0" \
258 "ide_ide=run ideargs addip addcons; " \
259 "disk 200000 0:1; bootm\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200260 "usb_self=run usbload; run ramargs addip addcons; " \
261 "bootm 200000 400000\0" \
262 "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
263 "usbboot 400000 0:2\0" \
264 "bootfile=uImage\0" \
265 "load=tftp 200000 $(u-boot)\0" \
266 "u-boot=u-boot.bin\0" \
267 "update=protect off FC000000 FC05FFFF;" \
268 "erase FC000000 FC05FFFF;" \
269 "cp.b 200000 FC000000 $(filesize);" \
270 "protect on FC000000 FC05FFFF\0" \
271 ""
272
273#define CONFIG_BOOTCOMMAND "run flash_self"
274
275/*
276 * IPB Bus clocking configuration.
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200279
280/*
281 * PCI Bus clocking configuration
282 *
283 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200285 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
288# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200289#endif
290
291/*
292 * I2C configuration
293 */
294#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200296
297/*
298 * I2C clock frequency
299 *
300 * Please notice, that the resulting clock frequency could differ from the
301 * configured value. This is because the I2C clock is derived from system
302 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200304 * approximation allways lies below the configured value, never above.
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
307#define CONFIG_SYS_I2C_SLAVE 0x7F
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200308
309/*
Wolfgang Denk610cf362006-05-03 01:24:04 +0200310 * EEPROM configuration for I²C EEPROM M24C32
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200311 * M24C64 should work also. For other EEPROMs config should be verified.
Wolfgang Denk610cf362006-05-03 01:24:04 +0200312 *
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200313 * The TQM5200 module may hold an EEPROM at address 0x50.
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
316#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
317#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
318#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200319
320/*
321 * RTC configuration
322 */
323#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
324# define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325# define CONFIG_SYS_I2C_RTC_ADDR 0x68
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200326#else
327# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
328# define CONFIG_BOARD_EARLY_INIT_R
329#endif
330
331/*
332 * Flash configuration
333 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200334#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200335
336/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200338#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
340#define CONFIG_SYS_FLASH_EMPTY_INFO
341#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
342#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
343#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#if !defined(CONFIG_SYS_LOWBOOT)
346#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
347#else /* CONFIG_SYS_LOWBOOT */
348#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
349#endif /* CONFIG_SYS_LOWBOOT */
350#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200351 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
353#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200354
355/* Dynamic MTD partition support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100356#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200357#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
358#define CONFIG_FLASH_CFI_MTD
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200359#define MTDIDS_DEFAULT "nor0=TQM5200-0"
360#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
361 "1408k(kernel)," \
362 "2m(initrd)," \
363 "4m(small-fs)," \
364 "16m(big-fs)," \
365 "8m(misc)"
366
367/*
368 * Environment settings
369 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200370#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200371#define CONFIG_ENV_SIZE 0x10000
372#define CONFIG_ENV_SECT_SIZE 0x20000
373#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
374#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200375
376/*
377 * Memory map
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_MBAR 0xF0000000
380#define CONFIG_SYS_SDRAM_BASE 0x00000000
381#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200382
383/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200385#ifdef CONFIG_POST
386/* preserve space for the post_word at end of on-chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200387# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200388#else
Wolfgang Denk553f0982010-10-26 13:32:32 +0200389# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200390#endif /*CONFIG_POST*/
391
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200392#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200394
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200395#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
397# define CONFIG_SYS_RAMBOOT 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200398#endif
399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
401#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
402#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200403
404/*
405 * Ethernet configuration
406 *
Ben Warren86321fc2009-02-05 23:58:25 -0800407 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200408 */
409#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800410#define CONFIG_MPC5xxx_FEC_MII100
411#undef CONFIG_MPC5xxx_MII10
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200412#define CONFIG_PHY_ADDR 0x00
413
414/*
415 * GPIO configuration on BC3450
416 *
Wolfgang Denk610cf362006-05-03 01:24:04 +0200417 * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
418 * PSC2: UART2 [0x xxxxxx4x]
419 * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
420 * PSC3: USB2 [0x xxxxx1xx]
421 * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
422 * (this has to match
423 * CONFIG_USB_CONFIG which is
424 * used by usb_ohci.c to set
425 * the USB ports)
426 * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
427 * (this is reset to '5'
428 * in FEC driver: fec.c)
429 * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
430 * ATA/CS: ??? [0x x1xxxxxx]
431 * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200432 * CS1: Use Pin gpio_wkup_6 as second
Wolfgang Denk610cf362006-05-03 01:24:04 +0200433 * SDRAM chip select (mem_cs1)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200434 * Timer: CAN2 / SPI
Wolfgang Denk610cf362006-05-03 01:24:04 +0200435 * I2C: CAN1 / I²C2 [0x bxxxxxxx]
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200436 */
437#ifdef CONFIG_BC3450_AC97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200439#else /* PSC2=UART2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200441#endif
442
443/*
444 * Miscellaneous configurable options
445 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_LONGHELP /* undef to save memory */
447#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500448#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200450#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200452#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
454#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
455#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200456
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200458 /* more extensive mem test */
459
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
461#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200464
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200466
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500468#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500470#endif
471
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200472/*
Jon Loeliger11799432007-07-10 09:02:57 -0500473 * Enable loopw command.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200474 */
475#define CONFIG_LOOPW
476
477/*
478 * Various low-level settings
479 */
Detlev Zundelfd428c02010-03-12 10:01:12 +0100480#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
481#define CONFIG_SYS_HID0_FINAL HID0_ICE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200482
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
484#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
485#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
486# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200487#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200489#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
491#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200492
493/* automatic configuration of chip selects */
494#ifdef CONFIG_TQM5200
495# define CONFIG_LAST_STAGE_INIT
496#endif /* CONFIG_TQM5200 */
497
498/*
499 * SRAM - Do not map below 2 GB in address space, because this area is used
500 * for SDRAM autosizing.
501 */
502#ifdef CONFIG_TQM5200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503# define CONFIG_SYS_CS2_START 0xE5000000
504# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
505# define CONFIG_SYS_CS2_CFG 0x0004D930
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200506#endif /* CONFIG_TQM5200 */
507
508/*
509 * Grafic controller - Do not map below 2 GB in address space, because this
510 * area is used for SDRAM autosizing.
511 */
512#ifdef CONFIG_TQM5200
513# define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
515# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
516# define CONFIG_SYS_CS1_CFG 0x8F48FF70
517# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200518#endif /* CONFIG_TQM5200 */
519
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_CS_BURST 0x00000000
521#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200522 /* flash and SM501 */
523
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_RESET_ADDRESS 0xff000000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200525
526/*
527 * USB stuff
528 */
529#define CONFIG_USB_CLOCK 0x0001BBBB
Wolfgang Denk610cf362006-05-03 01:24:04 +0200530#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200531
532/*
533 * IDE/ATA stuff Supports IDE harddisk
534 */
535#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
536
Wolfgang Denk610cf362006-05-03 01:24:04 +0200537#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
538#undef CONFIG_IDE_LED /* LED for ide not supported */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200539
Wolfgang Denk610cf362006-05-03 01:24:04 +0200540#define CONFIG_IDE_RESET /* reset for ide supported */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200541#define CONFIG_IDE_PREINIT
542
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
544#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200545
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200547
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200549
550/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200552
553/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200555
556/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200558
559/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_ATA_STRIDE 4
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200561
562#endif /* __CONFIG_H */