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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkbfc81252006-03-06 13:03:37 +010015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
stroesea20b27a2004-12-16 18:05:42 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2004 esd gmbh Hannover
30 *
31 *
32 * from db64360.h file
33 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
34 *
35 ************************************************************************/
36
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
stroesea20b27a2004-12-16 18:05:42 +000041/* This define must be before the core.h include */
42#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
43
44#ifndef __ASSEMBLY__
45#include <../board/Marvell/include/core.h>
46#endif
47/*-----------------------------------------------------*/
48
49#include "../board/esd/cpci750/local.h"
50
51/*
52 * High Level Configuration Options
53 * (easy to change)
54 */
55
56#define CONFIG_750FX /* we have a 750FX (override local.h) */
57
58#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
59
Wolfgang Denk2ae18242010-10-06 09:05:45 +020060#define CONFIG_SYS_TEXT_BASE 0xfff00000
61
Wolfgang Denkbfc81252006-03-06 13:03:37 +010062#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
stroesea20b27a2004-12-16 18:05:42 +000063
Reinhard Arlt0738e242010-04-13 09:59:09 +020064#define CONFIG_MV64360_ECC /* enable ECC support */
stroesea20b27a2004-12-16 18:05:42 +000065
Becky Bruce31d82672008-05-08 19:02:12 -050066#define CONFIG_HIGH_BATS 1 /* High BATs supported */
67
stroesea20b27a2004-12-16 18:05:42 +000068/* which initialization functions to call for this board */
69#define CONFIG_MISC_INIT_R
70#define CONFIG_BOARD_PRE_INIT
71#define CONFIG_BOARD_EARLY_INIT_F 1
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_BOARD_NAME "CPCI750"
stroesea20b27a2004-12-16 18:05:42 +000074#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
75
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076/*#define CONFIG_SYS_HUSH_PARSER*/
77#define CONFIG_SYS_HUSH_PARSER
stroesea20b27a2004-12-16 18:05:42 +000078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +000080
Stefan Roese0a14d6b2009-06-04 13:35:35 +020081#define CONFIG_CMDLINE_EDITING /* add command line history */
82#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Stefan Roesea7b9fb92006-01-18 20:05:34 +010083
stroesea20b27a2004-12-16 18:05:42 +000084/* Define which ETH port will be used for connecting the network */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_ETH_PORT ETH_0
stroesea20b27a2004-12-16 18:05:42 +000086
87/*
88 * The following defines let you select what serial you want to use
89 * for your console driver.
90 *
91 * what to do:
Wolfgang Denkbfc81252006-03-06 13:03:37 +010092 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
stroesea20b27a2004-12-16 18:05:42 +000094 * to 0 below.
95 *
96 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
97 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
98 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +010099#define CONFIG_MPSC
stroesea20b27a2004-12-16 18:05:42 +0000100#define CONFIG_MPSC_PORT 0
101
102/* to change the default ethernet port, use this define (options: 0, 1, 2) */
103#define CONFIG_NET_MULTI
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100104#define MV_ETH_DEVS 1
stroesea20b27a2004-12-16 18:05:42 +0000105#define CONFIG_ETHER_PORT 0
106
107#undef CONFIG_ETHER_PORT_MII /* use RMII */
108
109#define CONFIG_BOOTDELAY 5 /* autoboot disabled */
110
111#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
112
113#define CONFIG_ZERO_BOOTDELAY_CHECK
114
115
116#undef CONFIG_BOOTARGS
117
118/* -----------------------------------------------------------------------------
119 * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
120 */
121
122#define CONFIG_IPADDR "192.168.0.185"
123
124#define CONFIG_SERIAL "AA000001"
125#define CONFIG_SERVERIP "10.0.0.79"
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100126#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
stroesea20b27a2004-12-16 18:05:42 +0000127
128#define CONFIG_TESTDRAMDATA y
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100129#define CONFIG_TESTDRAMADDRESS n
stroesea20b27a2004-12-16 18:05:42 +0000130#define CONFIG_TESETDRAMWALK n
131
132/* ----------------------------------------------------------------------------- */
133
134
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100135#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
stroesea20b27a2004-12-16 18:05:42 +0000137
138#undef CONFIG_WATCHDOG /* watchdog disabled */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100139#undef CONFIG_ALTIVEC /* undef to disable */
stroesea20b27a2004-12-16 18:05:42 +0000140
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500141/*
142 * BOOTP options
143 */
144#define CONFIG_BOOTP_SUBNETMASK
145#define CONFIG_BOOTP_GATEWAY
146#define CONFIG_BOOTP_HOSTNAME
147#define CONFIG_BOOTP_BOOTPATH
148#define CONFIG_BOOTP_BOOTFILESIZE
stroesea20b27a2004-12-16 18:05:42 +0000149
150
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500151/*
152 * Command line configuration.
153 */
154#include <config_cmd_default.h>
155
Wolfgang Denk5728be32007-08-06 01:01:49 +0200156#define CONFIG_CMD_ASKENV
157#define CONFIG_CMD_I2C
158#define CONFIG_CMD_CACHE
159#define CONFIG_CMD_EEPROM
160#define CONFIG_CMD_PCI
161#define CONFIG_CMD_ELF
162#define CONFIG_CMD_DATE
163#define CONFIG_CMD_NET
164#define CONFIG_CMD_PING
165#define CONFIG_CMD_IDE
166#define CONFIG_CMD_FAT
167#define CONFIG_CMD_EXT2
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500168
stroesea20b27a2004-12-16 18:05:42 +0000169
170#define CONFIG_DOS_PARTITION
171
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100172#define CONFIG_USE_CPCIDVI
173
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100174#ifdef CONFIG_USE_CPCIDVI
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100175#define CONFIG_VIDEO
176#define CONFIG_VIDEO_CT69000
177#define CONFIG_CFB_CONSOLE
178#define CONFIG_VIDEO_SW_CURSOR
179#define CONFIG_VIDEO_LOGO
180#define CONFIG_I8042_KBD
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_ISA_IO 0
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100182#endif
183
stroesea20b27a2004-12-16 18:05:42 +0000184/*
185 * Miscellaneous configurable options
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
188#define CONFIG_SYS_I2C_MULTI_EEPROMS
189#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */
stroesea20b27a2004-12-16 18:05:42 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
192#define CONFIG_SYS_LONGHELP /* undef to save memory */
193#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500194#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000196#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000198#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
200#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
201#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203/*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */
204/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
205/*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000206
207/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_DRAM_TEST
stroesea20b27a2004-12-16 18:05:42 +0000209 * DRAM tests
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210 * CONFIG_SYS_DRAM_TEST - enables the following tests.
stroesea20b27a2004-12-16 18:05:42 +0000211 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212 * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100213 * Environment variable 'test_dram_data' must be
214 * set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100216 * addressable. Environment variable
217 * 'test_dram_address' must be set to 'y'.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100219 * This test takes about 6 minutes to test 64 MB.
220 * Environment variable 'test_dram_walk' must be
221 * set to 'y'.
stroesea20b27a2004-12-16 18:05:42 +0000222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_DRAM_TEST
224#if defined(CONFIG_SYS_DRAM_TEST)
225#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
226/*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
227#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
228#define CONFIG_SYS_DRAM_TEST_DATA
229#define CONFIG_SYS_DRAM_TEST_ADDRESS
230#define CONFIG_SYS_DRAM_TEST_WALK
231#endif /* CONFIG_SYS_DRAM_TEST */
stroesea20b27a2004-12-16 18:05:42 +0000232
233#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
stroesea20b27a2004-12-16 18:05:42 +0000235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
stroesea20b27a2004-12-16 18:05:42 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200239#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
stroesea20b27a2004-12-16 18:05:42 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
stroesea20b27a2004-12-16 18:05:42 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_TCLK 133000000
stroesea20b27a2004-12-16 18:05:42 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245/*#define CONFIG_SYS_750FX_HID0 0x8000c084*/
246#define CONFIG_SYS_750FX_HID0 0x80008484
247#define CONFIG_SYS_750FX_HID1 0x54800000
248#define CONFIG_SYS_750FX_HID2 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000249
250/*
251 * Low Level Configuration Settings
252 * (address mappings, register initial values, etc.)
253 * You should know what you are doing if you make changes here.
254 */
255
256/*-----------------------------------------------------------------------
257 * Definitions for initial stack pointer and data area
258 */
259
260 /*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
stroesea20b27a2004-12-16 18:05:42 +0000262 * To an unused memory region. The stack will remain in cache until RAM
263 * is initialized
264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#undef CONFIG_SYS_INIT_RAM_LOCK
266/* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
267/* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
268#define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200269#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200270#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
stroesea20b27a2004-12-16 18:05:42 +0000271
272#define RELOCATE_INTERNAL_RAM_ADDR
273#ifdef RELOCATE_INTERNAL_RAM_ADDR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
275#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000
stroesea20b27a2004-12-16 18:05:42 +0000276#endif
277
278/*-----------------------------------------------------------------------
279 * Start addresses for the final memory configuration
280 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_SDRAM_BASE 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000284/* Dummies for BAT 4-7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
286#define CONFIG_SYS_SDRAM2_BASE 0x20000000
287#define CONFIG_SYS_SDRAM3_BASE 0x30000000
288#define CONFIG_SYS_SDRAM4_BASE 0x40000000
289#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
290#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
291#define CONFIG_SYS_MONITOR_BASE 0xfff00000
292#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
stroesea20b27a2004-12-16 18:05:42 +0000293
294/*-----------------------------------------------------------------------
295 * FLASH related
296 *----------------------------------------------------------------------*/
297
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200298#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
300#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
301#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
302#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */
303#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
304#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */
305#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
306#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
307 CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \
308 CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \
309 CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
310#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
stroesea20b27a2004-12-16 18:05:42 +0000311
312/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_DRAM_BANKS 4
stroesea20b27a2004-12-16 18:05:42 +0000314
315/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
stroesea20b27a2004-12-16 18:05:42 +0000317
318/* Peripheral Device section */
319
320/*******************************************************/
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100321/* We have on the cpci750 Board : */
322/* GT-Chipset Register Area */
323/* GT-Chipset internal SRAM 256k */
324/* SRAM on external device module */
325/* Real time clock on external device module */
326/* dobble UART on external device module */
327/* Data flash on external device module */
328/* Boot flash on external device module */
stroesea20b27a2004-12-16 18:05:42 +0000329/*******************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
331#define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
stroesea20b27a2004-12-16 18:05:42 +0000332
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100333#undef MARVEL_STANDARD_CFG
334#ifndef MARVEL_STANDARD_CFG
stroesea20b27a2004-12-16 18:05:42 +0000335/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
337/*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
338#define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
stroesea20b27a2004-12-16 18:05:42 +0000339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
341#define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
342#define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
343#define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
344#define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
stroesea20b27a2004-12-16 18:05:42 +0000345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */
347#define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */
348#define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */
349#define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */
350#define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */
stroesea20b27a2004-12-16 18:05:42 +0000351
352/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
353#endif
354
355/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
357#define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
358#define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
359#define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */
360#define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
stroesea20b27a2004-12-16 18:05:42 +0000361
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100362 /* c 4 a 8 2 4 1 c */
363 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
wdenkefe2a4d2004-12-16 21:44:03 +0000364 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
365 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
366 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
stroesea20b27a2004-12-16 18:05:42 +0000367
368
369/* MPP Control MV64360 Appendix P P. 632*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */
371#define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */
372#define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */
373#define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */
374/* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */
stroesea20b27a2004-12-16 18:05:42 +0000375
376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
stroesea20b27a2004-12-16 18:05:42 +0000378
379/* setup new config_value for MV64360 DDR-RAM To_do !! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
381/*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
stroesea20b27a2004-12-16 18:05:42 +0000382 /* GB has high prio.
383 idma has low prio
384 MPSC has low prio
385 pci has low prio 1 and 2
386 cpu has high prio
387 Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
388 ECC disable
389 non registered DRAM */
390 /* 31:26 25:22 21:20 19 18 17 16 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100391 /* 100001 0000 010 0 0 0 0 */
stroesea20b27a2004-12-16 18:05:42 +0000392 /* refresh_count=0x400
393 phisical interleaving disable
394 virtual interleaving enable */
395 /* 15 14 13:0 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100396 /* 0 1 0x400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397# define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
stroesea20b27a2004-12-16 18:05:42 +0000398
399
400/*-----------------------------------------------------------------------
401 * PCI stuff
402 *-----------------------------------------------------------------------
403 */
404
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100405#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
406#define PCI_HOST_FORCE 1 /* configure as pci host */
407#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroesea20b27a2004-12-16 18:05:42 +0000408
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100409#define CONFIG_PCI /* include pci support */
410#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
411#define CONFIG_PCI_PNP /* do pci plug-and-play */
412#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
stroesea20b27a2004-12-16 18:05:42 +0000413
414/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
416#define CONFIG_SYS_PCI0_MEM_SIZE _128M
417#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
418#define CONFIG_SYS_PCI1_MEM_SIZE _128M
stroesea20b27a2004-12-16 18:05:42 +0000419
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
421#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
stroesea20b27a2004-12-16 18:05:42 +0000422
stroesea20b27a2004-12-16 18:05:42 +0000423/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
425#define CONFIG_SYS_PCI0_IO_SIZE _16M
426#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
427#define CONFIG_SYS_PCI1_IO_SIZE _16M
stroesea20b27a2004-12-16 18:05:42 +0000428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
430#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
431#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
432#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
Stefan Roesea7b9fb92006-01-18 20:05:34 +0100435
stroesea20b27a2004-12-16 18:05:42 +0000436#if defined (CONFIG_750CX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_PCI_IDSEL 0x0
stroesea20b27a2004-12-16 18:05:42 +0000438#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_PCI_IDSEL 0x30
stroesea20b27a2004-12-16 18:05:42 +0000440#endif
441
442/*-----------------------------------------------------------------------
443 * IDE/ATA stuff
444 *-----------------------------------------------------------------------
445 */
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100446#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
447#undef CONFIG_IDE_LED /* no led for ide supported */
448#define CONFIG_IDE_RESET /* no reset for ide supported */
449#define CONFIG_IDE_PREINIT /* check for units */
stroesea20b27a2004-12-16 18:05:42 +0000450
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */
452#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000453
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_ATA_BASE_ADDR 0
455#define CONFIG_SYS_ATA_IDE0_OFFSET 0
456#define CONFIG_SYS_ATA_IDE1_OFFSET 0
stroesea20b27a2004-12-16 18:05:42 +0000457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
459#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
460#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000461
462
463/*----------------------------------------------------------------------
464 * Initial BAT mappings
465 */
466
467/* NOTES:
468 * 1) GUARDED and WRITE_THRU not allowed in IBATS
469 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
470 */
471
472/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
474#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
475#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
476#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
stroesea20b27a2004-12-16 18:05:42 +0000477
478/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
480#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
481#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
482#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
stroesea20b27a2004-12-16 18:05:42 +0000483
484/* PCI0, PCI1 in one BAT */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
486#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
487#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
488#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
stroesea20b27a2004-12-16 18:05:42 +0000489
490/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
492#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
493#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
494#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
stroesea20b27a2004-12-16 18:05:42 +0000495
496/*
497 * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
498 * IBAT4 and DBAT4
499 * FIXME: ingo disable BATs for Linux Kernel
500 */
501#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */
502/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */
503
504#ifdef SETUP_HIGH_BATS_FX750
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
506#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
507#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
508#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000509
510/* IBAT5 and DBAT5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
512#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
513#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
514#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
stroesea20b27a2004-12-16 18:05:42 +0000515
516/* IBAT6 and DBAT6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
518#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
519#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
520#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
stroesea20b27a2004-12-16 18:05:42 +0000521
522/* IBAT7 and DBAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
524#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
525#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
526#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
stroesea20b27a2004-12-16 18:05:42 +0000527
528#else /* set em out of range for Linux !!!!!!!!!!! */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
530#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
531#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
532#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000533
534/* IBAT5 and DBAT5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
536#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
537#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
538#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000539
540/* IBAT6 and DBAT6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
542#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
543#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
544#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000545
546/* IBAT7 and DBAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
548#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
549#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
550#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
stroesea20b27a2004-12-16 18:05:42 +0000551
552#endif
553/* FIXME: ingo end: disable BATs for Linux Kernel */
554
555/* I2C addresses for the two DIMM SPD chips */
556#define DIMM0_I2C_ADDR 0x51
557#define DIMM1_I2C_ADDR 0x52
558
559/*
560 * For booting Linux, the board info and command line data
561 * have to be in the first 8 MB of memory, since this is
562 * the maximum mapped by the Linux kernel during initialization.
563 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000565
566/*-----------------------------------------------------------------------
567 * FLASH organization
568 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
stroesea20b27a2004-12-16 18:05:42 +0000570
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200571#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
572#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
573#define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000574
575#if 0
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200576#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200577#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
578#define CONFIG_ENV_SECT_SIZE 0x10000
579#define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580/* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
stroesea20b27a2004-12-16 18:05:42 +0000581#endif
582
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200583#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
585#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
586#define CONFIG_SYS_I2C_EEPROM_ADDR 0x050
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200587#define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
588#define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000589
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
591#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
592#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
stroesea20b27a2004-12-16 18:05:42 +0000593
594/*-----------------------------------------------------------------------
595 * Cache Configuration
596 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500598#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200599#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
stroesea20b27a2004-12-16 18:05:42 +0000600#endif
601
602/*-----------------------------------------------------------------------
603 * L2CR setup -- make sure this is right for your board!
604 * look in include/mpc74xx.h for the defines used here
605 */
606
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607/*#define CONFIG_SYS_L2*/
608#undef CONFIG_SYS_L2
stroesea20b27a2004-12-16 18:05:42 +0000609
610/* #ifdef CONFIG_750CX*/
611#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
612#define L2_INIT 0
613#else
Wolfgang Denkbfc81252006-03-06 13:03:37 +0100614#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
stroesea20b27a2004-12-16 18:05:42 +0000615 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
616#endif
617
618#define L2_ENABLE (L2_INIT | L2CR_L2E)
619
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_BOARD_ASM_INIT 1
stroesea20b27a2004-12-16 18:05:42 +0000621
Stefan Roese58f10462009-06-04 13:35:39 +0200622#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
Reinhard Arlt0738e242010-04-13 09:59:09 +0200623#define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
624#define CONFIG_SYS_PLD_VER 0xf0e00000
Stefan Roese58f10462009-06-04 13:35:39 +0200625
stroesea20b27a2004-12-16 18:05:42 +0000626#endif /* __CONFIG_H */