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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +02002/*
3 * am335x_sl50.h
4 *
5 * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +02006 */
7
8#ifndef __CONFIG_AM335X_EVM_H
9#define __CONFIG_AM335X_EVM_H
10
11#include <configs/ti_am335x_common.h>
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020012
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020013#define CONFIG_SYS_BOOTM_LEN (16 << 20)
14
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020015/* Clock Defines */
16#define V_OSCK 24000000 /* Clock output from T2 */
17#define V_SCLK (V_OSCK)
18
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020019#ifndef CONFIG_SPL_BUILD
20
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020021#define MEM_LAYOUT_ENV_SETTINGS \
22 "scriptaddr=0x80000000\0" \
23 "pxefile_addr_r=0x80100000\0" \
24 "kernel_addr_r=0x82000000\0" \
25 "fdt_addr_r=0x88000000\0" \
26 "ramdisk_addr_r=0x88080000\0" \
27
28#define BOOT_TARGET_DEVICES(func) \
29 func(MMC, mmc, 0) \
30 func(MMC, mmc, 1)
31
32#define AM335XX_BOARD_FDTFILE \
33 "fdtfile=am335x-sl50.dtb\0" \
34
35#include <config_distro_bootcmd.h>
36
37#define CONFIG_EXTRA_ENV_SETTINGS \
38 AM335XX_BOARD_FDTFILE \
39 MEM_LAYOUT_ENV_SETTINGS \
40 BOOTENV
41
42#endif
43
44/* NS16550 Configuration */
45#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
46#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
47#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
48#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
49#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
50#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020051
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020052/* PMIC support */
53#define CONFIG_POWER_TPS65217
54#define CONFIG_POWER_TPS65910
55
56/* SPL */
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020057
58/* Bootcount using the RTC block */
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020059#define CONFIG_SYS_BOOTCOUNT_BE
60
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020061/* Network. */
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +020062
63#endif /* ! __CONFIG_AM335X_SL50_H */