blob: d12963a5f0b35ef017fab877f6adb18709f7ad82 [file] [log] [blame]
Chong Huangdbb6d362010-11-30 03:36:23 -05001/*
2 * U-boot - Configuration file for bf525-ucr2 board
3 * The board includes ADSP-BF525 rev. 0.2,
4 * 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
5 * USB 2.0 High Speed OTG USB WIFI,
6 * SPI flash (cFeon EN25Q128 16 MB),
7 * Support PPI and ITU-R656,
8 * See http://www.ucrobotics.com/?q=cn/ucr2
9 */
10
11#ifndef __CONFIG_BF525_UCR2_H__
12#define __CONFIG_BF525_UCR2_H__
13
14#include <asm/config-pre.h>
15
16/*
17 * Processor Settings
18 */
19#define CONFIG_BFIN_CPU bf525-0.2
20#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
21
22/*
23 * Clock Settings
24 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
25 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
26 */
27/* CONFIG_CLKIN_HZ is any value in Hz */
28#define CONFIG_CLKIN_HZ 24000000
29/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
30/* 1 = CLKIN / 2 */
31#define CONFIG_CLKIN_HALF 0
32/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
33/* 1 = bypass PLL */
34#define CONFIG_PLL_BYPASS 0
35/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
36/* Values can range from 0-63 (where 0 means 64) */
37#define CONFIG_VCO_MULT 20
38/* CCLK_DIV controls the core clock divider */
39/* Values can be 1, 2, 4, or 8 ONLY */
40#define CONFIG_CCLK_DIV 1
41/* SCLK_DIV controls the system clock divider */
42/* Values can range from 1-15 */
43#define CONFIG_SCLK_DIV 4
44
45/*
46 * Memory Settings
47 */
48#define CONFIG_MEM_ADD_WDTH 9
49#define CONFIG_MEM_SIZE 32
50
51/*
52 * SDRAM reference page
53 * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
54 */
55#define CONFIG_EBIU_SDRRC_VAL 0x3f8
56#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
57
58#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
59#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
60#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
61
62#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
63#define CONFIG_SYS_MALLOC_LEN (320 * 1024)
64
65/* We don't have a parallel flash chip */
66#define CONFIG_SYS_NO_FLASH
67
68/* support for serial flash */
69#define CONFIG_BFIN_SPI
Chong Huangdbb6d362010-11-30 03:36:23 -050070#define CONFIG_CMD_SF
71#define CONFIG_SF_DEFAULT_HZ 30000000
Chong Huangdbb6d362010-11-30 03:36:23 -050072
73#define CONFIG_ENV_IS_IN_SPI_FLASH
74#define CONFIG_ENV_SPI_MAX_HZ 30000000
75#define CONFIG_ENV_OFFSET 0x10000
76#define CONFIG_ENV_SIZE 0x10000
77#define CONFIG_ENV_SECT_SIZE 0x10000
78#define CONFIG_ENV_OVERWRITE 1
79
80/*
81 * Misc Settings
82 */
83#define CONFIG_UART_CONSOLE 0
84
85#define CONFIG_BAUDRATE 115200
Sonic Zhang7a58eb92013-11-18 14:50:19 +080086#define CONFIG_BFIN_SERIAL
Chong Huangdbb6d362010-11-30 03:36:23 -050087#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
88#define CONFIG_BOOTCOMMAND "run sfboot"
89#define CONFIG_BOOTDELAY 5
90#define CONFIG_EXTRA_ENV_SETTINGS \
91 "sfboot=sf probe 1;" \
92 "sf read 0x1000000 0x20000 0x300000;" \
93 "bootm 0x1000000\0"
94
Chong Huangdbb6d362010-11-30 03:36:23 -050095#endif