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Stefan Roese2bae75a2015-04-25 06:29:56 +02001/*
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _CONFIG_DB_88F6820_GP_H
8#define _CONFIG_DB_88F6820_GP_H
9
10/*
11 * High Level Configuration Options (easy to change)
12 */
Stefan Roese2bae75a2015-04-25 06:29:56 +020013
Stefan Roese2bae75a2015-04-25 06:29:56 +020014#define CONFIG_DISPLAY_BOARDINFO_LATE
15
Stefan Roese2923c2d2015-08-06 14:27:36 +020016/*
17 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
18 * for DDR ECC byte filling in the SPL before loading the main
19 * U-Boot into it.
20 */
21#define CONFIG_SYS_TEXT_BASE 0x00800000
Stefan Roese2bae75a2015-04-25 06:29:56 +020022#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
23
24/*
25 * Commands configuration
26 */
Stefan Roesece2cb1d2015-08-11 12:50:58 +020027#define CONFIG_CMD_PCI
Stefan Roese2bae75a2015-04-25 06:29:56 +020028
29/* I2C */
30#define CONFIG_SYS_I2C
31#define CONFIG_SYS_I2C_MVTWSI
32#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
33#define CONFIG_SYS_I2C_SLAVE 0x0
34#define CONFIG_SYS_I2C_SPEED 100000
35
36/* SPI NOR flash default params, used by sf commands */
37#define CONFIG_SF_DEFAULT_SPEED 1000000
38#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Stefan Roese2bae75a2015-04-25 06:29:56 +020039
Stefan Roesee80f1e82015-06-29 14:58:11 +020040/*
41 * SDIO/MMC Card Configuration
42 */
Stefan Roesee80f1e82015-06-29 14:58:11 +020043#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
44
Stefan Roese7cbaff92015-06-29 14:58:14 +020045/*
46 * SATA/SCSI/AHCI configuration
47 */
48#define CONFIG_LIBATA
49#define CONFIG_SCSI_AHCI
50#define CONFIG_SCSI_AHCI_PLAT
51#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
52#define CONFIG_SYS_SCSI_MAX_LUN 1
53#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
54 CONFIG_SYS_SCSI_MAX_LUN)
55
Stefan Roesee80f1e82015-06-29 14:58:11 +020056/* Partition support */
Stefan Roesee80f1e82015-06-29 14:58:11 +020057
58/* Additional FS support/configuration */
59#define CONFIG_SUPPORT_VFAT
60
Stefan Roese59565732015-06-29 14:58:16 +020061/* USB/EHCI configuration */
Stefan Roese59565732015-06-29 14:58:16 +020062#define CONFIG_EHCI_IS_TDI
63
Stefan Roese2bae75a2015-04-25 06:29:56 +020064/* Environment in SPI NOR flash */
Stefan Roese2bae75a2015-04-25 06:29:56 +020065#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
66#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
67#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
68
69#define CONFIG_PHY_MARVELL /* there is a marvell phy */
Stefan Roese2bae75a2015-04-25 06:29:56 +020070#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
71
Stefan Roesece2cb1d2015-08-11 12:50:58 +020072/* PCIe support */
Stefan Roese64512232015-11-25 07:37:00 +010073#ifndef CONFIG_SPL_BUILD
Stefan Roesece2cb1d2015-08-11 12:50:58 +020074#define CONFIG_PCI_MVEBU
Stefan Roesece2cb1d2015-08-11 12:50:58 +020075#define CONFIG_PCI_SCAN_SHOW
Stefan Roese64512232015-11-25 07:37:00 +010076#endif
Stefan Roesece2cb1d2015-08-11 12:50:58 +020077
Stefan Roese2bae75a2015-04-25 06:29:56 +020078#define CONFIG_SYS_ALT_MEMTEST
79
Kevin Smith3fd38af2015-05-18 16:09:46 +000080/* Keep device tree and initrd in lower memory so the kernel can access them */
81#define CONFIG_EXTRA_ENV_SETTINGS \
82 "fdt_high=0x10000000\0" \
83 "initrd_high=0x10000000\0"
84
Stefan Roese9e30b312015-03-25 13:35:15 +010085/* SPL */
Stefan Roese7853c502015-07-20 11:20:40 +020086/*
87 * Select the boot device here
88 *
89 * Currently supported are:
90 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
91 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
92 */
93#define SPL_BOOT_SPI_NOR_FLASH 1
94#define SPL_BOOT_SDIO_MMC_CARD 2
95#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
96
Stefan Roese9e30b312015-03-25 13:35:15 +010097/* Defines for SPL */
98#define CONFIG_SPL_FRAMEWORK
99#define CONFIG_SPL_SIZE (140 << 10)
100#define CONFIG_SPL_TEXT_BASE 0x40000030
101#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
102
103#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
104#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
105
Stefan Roese64512232015-11-25 07:37:00 +0100106#ifdef CONFIG_SPL_BUILD
107#define CONFIG_SYS_MALLOC_SIMPLE
108#endif
Stefan Roese9e30b312015-03-25 13:35:15 +0100109
110#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
111#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
112
Stefan Roese7853c502015-07-20 11:20:40 +0200113#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
Stefan Roese9e30b312015-03-25 13:35:15 +0100114/* SPL related SPI defines */
Stefan Roese9e30b312015-03-25 13:35:15 +0100115#define CONFIG_SPL_SPI_LOAD
Stefan Roese09a54c02015-11-20 13:51:57 +0100116#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
Stefan Roese7853c502015-07-20 11:20:40 +0200117#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
118#endif
119
120#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
121/* SPL related MMC defines */
Stefan Roese7853c502015-07-20 11:20:40 +0200122#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
123#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
Stefan Roese7853c502015-07-20 11:20:40 +0200124#ifdef CONFIG_SPL_BUILD
125#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
126#endif
127#endif
Stefan Roese9e30b312015-03-25 13:35:15 +0100128
Stefan Roese2bae75a2015-04-25 06:29:56 +0200129/*
130 * mv-common.h should be defined after CMD configs since it used them
131 * to enable certain macros
132 */
133#include "mv-common.h"
134
135#endif /* _CONFIG_DB_88F6820_GP_H */