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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 14d0a02a168b36e87665b8d7f42fa3e88263d26d / . / include / configs / XPEDITE5200.h
blob: 7ff440e247466d2f8b0ca429d0a5228f7c9831fb [file] [log] [blame]
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]1/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * xpedite5200 board configuration file
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8548 1
37#define CONFIG_XPEDITE5200 1
38#define CONFIG_SYS_BOARD_NAME "XPedite5200"
39#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]40
41#define CONFIG_PCI 1 /* Enable PCI/PCIE */
42#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
43#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
44#define CONFIG_PCI1 1 /* PCI controller 1 */
45#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
46#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
47#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
48
49/*
50 * DDR config
51 */
52#define CONFIG_FSL_DDR2
53#undef CONFIG_FSL_DDR_INTERACTIVE
54#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
55#define CONFIG_DDR_SPD
56#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
57#define SPD_EEPROM_ADDRESS 0x54
58#define CONFIG_NUM_DDR_CONTROLLERS 1
59#define CONFIG_DIMM_SLOTS_PER_CTLR 1
60#define CONFIG_CHIP_SELECTS_PER_CTRL 2
61#define CONFIG_DDR_ECC
62#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
63#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
64#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
65#define CONFIG_VERY_BIG_RAM
66
67#define CONFIG_SYS_CLK_FREQ 66666666
68
69/*
70 * These can be toggled for performance analysis, otherwise use default.
71 */
72#define CONFIG_L2_CACHE /* toggle L2 cache */
73#define CONFIG_BTB /* toggle branch predition */
74#define CONFIG_ENABLE_36BIT_PHYS 1
75
76/*
77 * Base addresses -- Note these are effective addresses where the
78 * actual resources get mapped (not physical addresses)
79 */
80#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
81#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
82#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
83#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]84
85/*
86 * Diagnostics
87 */
88#define CONFIG_SYS_ALT_MEMTEST
89#define CONFIG_SYS_MEMTEST_START 0x10000000
90#define CONFIG_SYS_MEMTEST_END 0x20000000
91
92/*
93 * Memory map
94 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
95 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
96 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
97 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
98 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
99 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
100 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
101 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
102 */
103
Kumar Gala202d9482009-09-15 22:21:58 -0500[diff] [blame]104#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]105
106/*
107 * NAND flash configuration
108 */
109#define CONFIG_SYS_NAND_BASE 0xef800000
110#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
111#define CONFIG_SYS_MAX_NAND_DEVICE 1
112#define CONFIG_NAND_ACTL
113#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
114#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
115#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
116#define CONFIG_SYS_NAND_ACTL_DELAY 25
117
118/*
119 * NOR flash configuration
120 */
121#define CONFIG_SYS_FLASH_BASE 0xfc000000
122#define CONFIG_SYS_FLASH_BASE2 0xf8000000
123#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
124#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
125#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
126#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
127#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
128#define CONFIG_FLASH_CFI_DRIVER
129#define CONFIG_SYS_FLASH_CFI
Peter Tyser5ff82102009-07-19 19:17:40 -0500[diff] [blame]130#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]131#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
132 {0xfbf40000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame^]133#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]134
135/*
136 * Chip select configuration
137 */
138/* NOR Flash 0 on CS0 */
139#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
140 BR_PS_16 | \
141 BR_V)
142#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
143 OR_GPCM_ACS_DIV4 | \
144 OR_GPCM_SCY_8)
145
146/* NOR Flash 1 on CS1 */
147#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
148 BR_PS_16 | \
149 BR_V)
150#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
151
152/* NAND flash on CS2 */
153#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
154 BR_PS_8 | \
155 BR_V)
156
157/* NAND flash on CS2 */
158#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
159 OR_GPCM_BCTLD | \
160 OR_GPCM_CSNT | \
161 OR_GPCM_ACS_DIV4 | \
162 OR_GPCM_SCY_4 | \
163 OR_GPCM_TRLX | \
164 OR_GPCM_EHTR)
165
166/* NAND flash on CS3 */
167#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
168 BR_PS_8 | \
169 BR_V)
170#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
171
172/*
173 * Use L1 as initial stack
174 */
175#define CONFIG_SYS_INIT_RAM_LOCK 1
176#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
177#define CONFIG_SYS_INIT_RAM_END 0x4000
178
179#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
180#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
181#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182
183#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
184#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
185
186/*
187 * Serial Port
188 */
189#define CONFIG_CONS_INDEX 1
190#define CONFIG_SYS_NS16550
191#define CONFIG_SYS_NS16550_SERIAL
192#define CONFIG_SYS_NS16550_REG_SIZE 1
193#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
194#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
195#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
196#define CONFIG_SYS_BAUDRATE_TABLE \
197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198#define CONFIG_BAUDRATE 115200
199#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
200#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
201
202/*
203 * Use the HUSH parser
204 */
205#define CONFIG_SYS_HUSH_PARSER
206#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
207
208/*
209 * Pass open firmware flat tree
210 */
211#define CONFIG_OF_LIBFDT 1
212#define CONFIG_OF_BOARD_SETUP 1
213#define CONFIG_OF_STDOUT_VIA_ALIAS 1
214
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]215/*
216 * I2C
217 */
218#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
219#define CONFIG_HARD_I2C /* I2C with hardware support */
220#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
221#define CONFIG_SYS_I2C_SLAVE 0x7F
222#define CONFIG_SYS_I2C_OFFSET 0x3000
223#define CONFIG_SYS_I2C2_OFFSET 0x3100
224#define CONFIG_I2C_MULTI_BUS
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]225
226/* I2C EEPROM */
227#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
228#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
229#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
230#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
231
232/* I2C RTC */
233#define CONFIG_RTC_M41T11 1
234#define CONFIG_SYS_I2C_RTC_ADDR 0x68
235#define CONFIG_SYS_M41T11_BASE_YEAR 2000
236
237/* GPIO */
238#define CONFIG_PCA953X
239#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
240#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
241#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
242
243/* PCA957 @ 0x18 */
244#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
245#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
246#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
247#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
248#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
249#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
250#define CONFIG_SYS_PCA953X_MONARCH 0x40
251#define CONFIG_SYS_PCA953X_EREADY 0x80
252
253/* PCA957 @ 0x19 */
254#define CONFIG_SYS_PCA953X_P14_IO0 0x01
255#define CONFIG_SYS_PCA953X_P14_IO1 0x02
256#define CONFIG_SYS_PCA953X_P14_IO2 0x04
257#define CONFIG_SYS_PCA953X_P14_IO3 0x08
258#define CONFIG_SYS_PCA953X_P14_IO4 0x10
259#define CONFIG_SYS_PCA953X_P14_IO5 0x20
260#define CONFIG_SYS_PCA953X_P14_IO6 0x40
261#define CONFIG_SYS_PCA953X_P14_IO7 0x80
262
263/*
264 * General PCI
265 * Memory space is mapped 1-1, but I/O space must start from 0.
266 */
267#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
268#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
269#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
270#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
271#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
272#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
273
274/*
275 * Networking options
276 */
277#define CONFIG_TSEC_ENET /* tsec ethernet support */
278#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
279#define CONFIG_NET_MULTI 1
280#define CONFIG_MII 1 /* MII PHY management */
281#define CONFIG_ETHPRIME "eTSEC1"
282
283#define CONFIG_TSEC1 1
284#define CONFIG_TSEC1_NAME "eTSEC1"
285#define TSEC1_FLAGS TSEC_GIGABIT
286#define TSEC1_PHY_ADDR 1
287#define TSEC1_PHYIDX 0
288#define CONFIG_HAS_ETH0
289
290#define CONFIG_TSEC2 1
291#define CONFIG_TSEC2_NAME "eTSEC2"
292#define TSEC2_FLAGS TSEC_GIGABIT
293#define TSEC2_PHY_ADDR 2
294#define TSEC2_PHYIDX 0
295#define CONFIG_HAS_ETH1
296
297#define CONFIG_TSEC3 1
298#define CONFIG_TSEC3_NAME "eTSEC3"
299#define TSEC3_FLAGS TSEC_GIGABIT
300#define TSEC3_PHY_ADDR 3
301#define TSEC3_PHYIDX 0
302#define CONFIG_HAS_ETH2
303
304#define CONFIG_TSEC4 1
305#define CONFIG_TSEC4_NAME "eTSEC4"
306#define TSEC4_FLAGS TSEC_GIGABIT
307#define TSEC4_PHY_ADDR 4
308#define TSEC4_PHYIDX 0
309#define CONFIG_HAS_ETH3
310
311/*
312 * BOOTP options
313 */
314#define CONFIG_BOOTP_BOOTFILESIZE
315#define CONFIG_BOOTP_BOOTPATH
316#define CONFIG_BOOTP_GATEWAY
317
318/*
319 * Command configuration.
320 */
321#include <config_cmd_default.h>
322
323#define CONFIG_CMD_ASKENV
324#define CONFIG_CMD_DATE
325#define CONFIG_CMD_DHCP
326#define CONFIG_CMD_EEPROM
327#define CONFIG_CMD_ELF
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500[diff] [blame]328#define CONFIG_CMD_SAVEENV
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]329#define CONFIG_CMD_FLASH
330#define CONFIG_CMD_I2C
331#define CONFIG_CMD_JFFS2
332#define CONFIG_CMD_MII
333#define CONFIG_CMD_NAND
334#define CONFIG_CMD_NET
335#define CONFIG_CMD_PCA953X
336#define CONFIG_CMD_PCA953X_INFO
337#define CONFIG_CMD_PCI
338#define CONFIG_CMD_PING
339#define CONFIG_CMD_SNTP
Becky Bruce199e2622010-06-17 11:37:25 -0500[diff] [blame]340#define CONFIG_CMD_REGINFO
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]341
342/*
343 * Miscellaneous configurable options
344 */
345#define CONFIG_SYS_LONGHELP /* undef to save memory */
346#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
347#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
349#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
350#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
351#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
352#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
353#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500[diff] [blame]354#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]355#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
356#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
357#define CONFIG_PANIC_HANG /* do not reset board on panic */
358#define CONFIG_PREBOOT /* enable preboot variable */
359#define CONFIG_FIT 1
360#define CONFIG_FIT_VERBOSE 1
361#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
362#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
363
364/*
365 * For booting Linux, the board info and command line data
366 * have to be in the first 16 MB of memory, since this is
367 * the maximum mapped by the Linux kernel during initialization.
368 */
369#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500[diff] [blame]370#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyser1f03cbf2008-12-23 16:32:00 -0600[diff] [blame]371
372/*
373 * Boot Flags
374 */
375#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
376#define BOOTFLAG_WARM 0x02 /* Software reboot */
377
378/*
379 * Environment Configuration
380 */
381#define CONFIG_ENV_IS_IN_FLASH 1
382#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
383#define CONFIG_ENV_SIZE 0x8000
384#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
385
386/*
387 * Flash memory map:
388 * fff80000 - ffffffff Pri U-Boot (512 KB)
389 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
390 * fff00000 - fff3ffff Pri FDT (256KB)
391 * fef00000 - ffefffff Pri OS image (16MB)
392 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
393 *
394 * fbf80000 - fbffffff Sec U-Boot (512 KB)
395 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
396 * fbf00000 - fbf3ffff Sec FDT (256KB)
397 * faf00000 - fbefffff Sec OS image (16MB)
398 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
399 */
400#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
401#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
402#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
403#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
404#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
405#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
406
407#define CONFIG_PROG_UBOOT1 \
408 "$download_cmd $loadaddr $ubootfile; " \
409 "if test $? -eq 0; then " \
410 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
411 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
412 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
413 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
414 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
415 "if test $? -ne 0; then " \
416 "echo PROGRAM FAILED; " \
417 "else; " \
418 "echo PROGRAM SUCCEEDED; " \
419 "fi; " \
420 "else; " \
421 "echo DOWNLOAD FAILED; " \
422 "fi;"
423
424#define CONFIG_PROG_UBOOT2 \
425 "$download_cmd $loadaddr $ubootfile; " \
426 "if test $? -eq 0; then " \
427 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
428 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
429 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
430 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
431 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
432 "if test $? -ne 0; then " \
433 "echo PROGRAM FAILED; " \
434 "else; " \
435 "echo PROGRAM SUCCEEDED; " \
436 "fi; " \
437 "else; " \
438 "echo DOWNLOAD FAILED; " \
439 "fi;"
440
441#define CONFIG_BOOT_OS_NET \
442 "$download_cmd $osaddr $osfile; " \
443 "if test $? -eq 0; then " \
444 "if test -n $fdtaddr; then " \
445 "$download_cmd $fdtaddr $fdtfile; " \
446 "if test $? -eq 0; then " \
447 "bootm $osaddr - $fdtaddr; " \
448 "else; " \
449 "echo FDT DOWNLOAD FAILED; " \
450 "fi; " \
451 "else; " \
452 "bootm $osaddr; " \
453 "fi; " \
454 "else; " \
455 "echo OS DOWNLOAD FAILED; " \
456 "fi;"
457
458#define CONFIG_PROG_OS1 \
459 "$download_cmd $osaddr $osfile; " \
460 "if test $? -eq 0; then " \
461 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
462 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
463 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
464 "if test $? -ne 0; then " \
465 "echo OS PROGRAM FAILED; " \
466 "else; " \
467 "echo OS PROGRAM SUCCEEDED; " \
468 "fi; " \
469 "else; " \
470 "echo OS DOWNLOAD FAILED; " \
471 "fi;"
472
473#define CONFIG_PROG_OS2 \
474 "$download_cmd $osaddr $osfile; " \
475 "if test $? -eq 0; then " \
476 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
477 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
478 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
479 "if test $? -ne 0; then " \
480 "echo OS PROGRAM FAILED; " \
481 "else; " \
482 "echo OS PROGRAM SUCCEEDED; " \
483 "fi; " \
484 "else; " \
485 "echo OS DOWNLOAD FAILED; " \
486 "fi;"
487
488#define CONFIG_PROG_FDT1 \
489 "$download_cmd $fdtaddr $fdtfile; " \
490 "if test $? -eq 0; then " \
491 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
492 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
493 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
494 "if test $? -ne 0; then " \
495 "echo FDT PROGRAM FAILED; " \
496 "else; " \
497 "echo FDT PROGRAM SUCCEEDED; " \
498 "fi; " \
499 "else; " \
500 "echo FDT DOWNLOAD FAILED; " \
501 "fi;"
502
503#define CONFIG_PROG_FDT2 \
504 "$download_cmd $fdtaddr $fdtfile; " \
505 "if test $? -eq 0; then " \
506 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
507 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
508 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
509 "if test $? -ne 0; then " \
510 "echo FDT PROGRAM FAILED; " \
511 "else; " \
512 "echo FDT PROGRAM SUCCEEDED; " \
513 "fi; " \
514 "else; " \
515 "echo FDT DOWNLOAD FAILED; " \
516 "fi;"
517
518#define CONFIG_EXTRA_ENV_SETTINGS \
519 "autoload=yes\0" \
520 "download_cmd=tftp\0" \
521 "console_args=console=ttyS0,115200\0" \
522 "root_args=root=/dev/nfs rw\0" \
523 "misc_args=ip=on\0" \
524 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
525 "bootfile=/home/user/file\0" \
526 "osfile=/home/user/uImage-XPedite5200\0" \
527 "fdtfile=/home/user/xpedite5200.dtb\0" \
528 "ubootfile=/home/user/u-boot.bin\0" \
529 "fdtaddr=c00000\0" \
530 "osaddr=0x1000000\0" \
531 "loadaddr=0x1000000\0" \
532 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
533 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
534 "prog_os1="CONFIG_PROG_OS1"\0" \
535 "prog_os2="CONFIG_PROG_OS2"\0" \
536 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
537 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
538 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
539 "bootcmd_flash1=run set_bootargs; " \
540 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
541 "bootcmd_flash2=run set_bootargs; " \
542 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
543 "bootcmd=run bootcmd_flash1\0"
544#endif /* __CONFIG_H */