blob: 78cab29e8c8526548665e75103d89f8fdfafc45e [file] [log] [blame]
Graeme Russc620c012008-12-07 10:28:57 +11001/*
2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Graeme Russbf165002010-04-24 00:05:47 +100024#include <asm/ibmpc.h>
Graeme Russc620c012008-12-07 10:28:57 +110025/*
26 * board/config.h - configuration options, board specific
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * Stuff still to be dealt with -
34 */
35#define CONFIG_RTC_MC146818
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define DEBUG_PARSER
42
43#define CONFIG_X86 1 /* Intel X86 CPU */
Graeme Russ6d83e3a2009-02-24 21:12:20 +110044#define CONFIG_SYS_SC520 1 /* AMD SC520 */
45#define CONFIG_SYS_SC520_SSI
Graeme Russc620c012008-12-07 10:28:57 +110046#define CONFIG_SHOW_BOOT_PROGRESS 1
47#define CONFIG_LAST_STAGE_INIT 1
48
49/*
50 * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
51 * bottom (processor) board MUST be removed!
52 */
53#undef CONFIG_WATCHDOG
Graeme Russ880c59e2010-04-24 00:05:58 +100054#define CONFIG_HW_WATCHDOG
Graeme Russc620c012008-12-07 10:28:57 +110055
56 /*-----------------------------------------------------------------------
Graeme Russbf165002010-04-24 00:05:47 +100057 * Serial Configuration
58 */
59#define CONFIG_SERIAL_MULTI
Graeme Russbf165002010-04-24 00:05:47 +100060#define CONFIG_CONS_INDEX 1
61#define CONFIG_SYS_NS16550
62#define CONFIG_SYS_NS16550_SERIAL
63#define CONFIG_SYS_NS16550_REG_SIZE 1
64#define CONFIG_SYS_NS16550_CLK 1843200
65#define CONFIG_BAUDRATE 9600
66#define CONFIG_SYS_BAUDRATE_TABLE \
67 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
68
69#define CONFIG_SYS_NS16550_COM1 UART0_BASE
70#define CONFIG_SYS_NS16550_COM2 UART1_BASE
71#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
72#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
73#define CONFIG_SYS_NS16550_PORT_MAPPED
74
75 /*-----------------------------------------------------------------------
Graeme Russc620c012008-12-07 10:28:57 +110076 * Video Configuration
77 */
78#undef CONFIG_VIDEO /* No Video Hardware */
79#undef CONFIG_CFB_CONSOLE
80
81/*
82 * Size of malloc() pool
83 */
Graeme Russb4feeb42009-11-24 20:04:13 +110084#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Graeme Russc620c012008-12-07 10:28:57 +110085
Graeme Russc620c012008-12-07 10:28:57 +110086/*-----------------------------------------------------------------------
87 * Command line configuration.
88 */
89#include <config_cmd_default.h>
90
Graeme Russc620c012008-12-07 10:28:57 +110091#define CONFIG_CMD_BDI /* bdinfo */
92#define CONFIG_CMD_BOOTD /* bootd */
93#define CONFIG_CMD_CONSOLE /* coninfo */
94#define CONFIG_CMD_ECHO /* echo arguments */
Graeme Russc620c012008-12-07 10:28:57 +110095#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
96#define CONFIG_CMD_FPGA /* FPGA configuration Support */
97#define CONFIG_CMD_IMI /* iminfo */
98#define CONFIG_CMD_IMLS /* List all found images */
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020099#define CONFIG_CMD_IRQ /* IRQ Information */
Graeme Russc620c012008-12-07 10:28:57 +1100100#define CONFIG_CMD_ITEST /* Integer (and string) test */
101#define CONFIG_CMD_LOADB /* loadb */
102#define CONFIG_CMD_LOADS /* loads */
103#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
104#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
Graeme Russ8fd80562010-04-24 00:05:55 +1000105#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
Graeme Russc620c012008-12-07 10:28:57 +1100106#undef CONFIG_CMD_NFS /* NFS support */
Graeme Russ5b34a292009-08-23 12:59:58 +1000107#define CONFIG_CMD_PCI /* PCI support */
Graeme Russ8fd80562010-04-24 00:05:55 +1000108#define CONFIG_CMD_PING /* ICMP echo support */
Graeme Russc620c012008-12-07 10:28:57 +1100109#define CONFIG_CMD_RUN /* run command in env variable */
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200110#define CONFIG_CMD_SAVEENV /* saveenv */
Graeme Russc620c012008-12-07 10:28:57 +1100111#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200112#define CONFIG_CMD_SOURCE /* "source" command Support */
Graeme Russc620c012008-12-07 10:28:57 +1100113#define CONFIG_CMD_XIMG /* Load part of Multi Image */
Graeme Russc620c012008-12-07 10:28:57 +1100114
115#define CONFIG_BOOTDELAY 15
116#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
117/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
118
119#if defined(CONFIG_CMD_KGDB)
120#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
121#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
122#endif
123
124/*
125 * Miscellaneous configurable options
126 */
127#define CONFIG_SYS_LONGHELP /* undef to save memory */
128#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
131 sizeof(CONFIG_SYS_PROMPT) + \
132 16) /* Print Buffer Size */
133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
135
136#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
137#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
138
Graeme Russc620c012008-12-07 10:28:57 +1100139#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
140
Graeme Russ4f197c32010-04-24 00:05:52 +1000141#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */
Graeme Russc620c012008-12-07 10:28:57 +1100142
Graeme Russc620c012008-12-07 10:28:57 +1100143/*-----------------------------------------------------------------------
144 * SDRAM Configuration
145 */
146#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
147#define CONFIG_NR_DRAM_BANKS 4
148
149/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
150#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
151#undef CONFIG_SYS_SDRAM_REFRESH_RATE
152#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
153#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
154#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
155
156/*-----------------------------------------------------------------------
157 * CPU Features
158 */
159#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
Graeme Russf2a55052010-04-24 00:05:57 +1000160#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
Graeme Russ6d83e3a2009-02-24 21:12:20 +1100161#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
162#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
163#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
Graeme Russc620c012008-12-07 10:28:57 +1100164#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
165 * in the SC520 on the CDP */
Graeme Russabf0cd32009-02-24 21:13:40 +1100166#define CONFIG_SYS_PCAT_INTERRUPTS
167#define CONFIG_SYS_NUM_IRQS 16
Graeme Russc620c012008-12-07 10:28:57 +1100168
169/*-----------------------------------------------------------------------
170 * Memory organization
171 */
172#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
173#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
174#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200175#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Graeme Russc620c012008-12-07 10:28:57 +1100176#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
177#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
178#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
179#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
180
181/* timeout values are in ticks */
182#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
183#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
184
185/* allow to overwrite serial and ethaddr */
186#define CONFIG_ENV_OVERWRITE
187
188 /*-----------------------------------------------------------------------
189 * FLASH configuration
190 */
191#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
192#define CONFIG_FLASH_CFI_LEGACY
193#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
194#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
195#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
196 CONFIG_SYS_FLASH_BASE_1, \
197 CONFIG_SYS_FLASH_BASE_2}
198#define CONFIG_SYS_FLASH_EMPTY_INFO
Graeme Russ6fd445c2010-04-24 00:05:51 +1000199#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Graeme Russc620c012008-12-07 10:28:57 +1100200#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
201#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
202#define CONFIG_SYS_FLASH_LEGACY_512Kx8
203
204 /*-----------------------------------------------------------------------
205 * Environment configuration
206 */
207#define CONFIG_ENV_IS_IN_FLASH 1
Graeme Russc620c012008-12-07 10:28:57 +1100208#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
Graeme Russf3a8d6b2009-08-23 12:59:48 +1000209#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
210#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
211/* Redundant Copy */
212#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
Graeme Russc620c012008-12-07 10:28:57 +1100213 CONFIG_ENV_SECT_SIZE)
Graeme Russf3a8d6b2009-08-23 12:59:48 +1000214#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
Graeme Russc620c012008-12-07 10:28:57 +1100215
216
217 /*-----------------------------------------------------------------------
218 * PCI configuration
219 */
Graeme Russ5b34a292009-08-23 12:59:58 +1000220#define CONFIG_PCI /* include pci support */
221#define CONFIG_PCI_PNP /* pci plug-and-play */
222#define CONFIG_SYS_FIRST_PCI_IRQ 10
223#define CONFIG_SYS_SECOND_PCI_IRQ 9
224#define CONFIG_SYS_THIRD_PCI_IRQ 11
225#define CONFIG_SYS_FORTH_PCI_IRQ 15
Graeme Russc620c012008-12-07 10:28:57 +1100226
Graeme Russ8fd80562010-04-24 00:05:55 +1000227 /*
228 * Network device (TRL8100B) support
229 */
230#define CONFIG_NET_MULTI
231#define CONFIG_RTL8139
232
Graeme Russc620c012008-12-07 10:28:57 +1100233/*-----------------------------------------------------------------------
Graeme Russc620c012008-12-07 10:28:57 +1100234 * FPGA configuration
235 */
236#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
237#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
238#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
239#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
240#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
241#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
242#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
243#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
244#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
245#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
246#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
247
248#ifndef __ASSEMBLER__
249extern unsigned long ip;
250
Graeme Russ141a62c2009-11-24 20:04:16 +1100251#define PRINTIP asm ("call 0\n" \
252 "0:\n" \
Graeme Russc620c012008-12-07 10:28:57 +1100253 "pop %%eax\n" \
254 "movl %%eax, %0\n" \
255 :"=r"(ip) \
256 : /* No Input Registers */ \
257 :"%eax"); \
258 printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
259
260#endif
261#endif /* __CONFIG_H */