blob: 7c37bd070156fab6b2fdc08988db436982e5bb94 [file] [log] [blame]
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +00001/*
2 * max98095.c -- MAX98095 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Maxim Integrated Products
5 *
6 * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Simon Glass150c5af2017-05-30 21:47:09 -060012
13#include <common.h>
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000014#include <asm/arch/clk.h>
15#include <asm/arch/cpu.h>
16#include <asm/arch/power.h>
17#include <asm/gpio.h>
18#include <asm/io.h>
19#include <common.h>
20#include <div64.h>
21#include <fdtdec.h>
22#include <i2c.h>
23#include <sound.h>
24#include "i2s.h"
25#include "max98095.h"
26
27enum max98095_type {
28 MAX98095,
29};
30
31struct max98095_priv {
32 enum max98095_type devtype;
33 unsigned int sysclk;
34 unsigned int rate;
35 unsigned int fmt;
36};
37
38static struct sound_codec_info g_codec_info;
39struct max98095_priv g_max98095_info;
40unsigned int g_max98095_i2c_dev_addr;
41
42/* Index 0 is reserved. */
43int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
44 88200, 96000};
45
46/*
47 * Writes value to a device register through i2c
48 *
49 * @param reg reg number to be write
50 * @param data data to be writen to the above registor
51 *
52 * @return int value 1 for change, 0 for no change or negative error code.
53 */
54static int max98095_i2c_write(unsigned int reg, unsigned char data)
55{
56 debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +053057 __func__, reg, data);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000058 return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1);
59}
60
61/*
62 * Read a value from a device register through i2c
63 *
64 * @param reg reg number to be read
65 * @param data address of read data to be stored
66 *
67 * @return int value 0 for success, -1 in case of error.
68 */
69static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data)
70{
71 int ret;
72
73 ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1);
74 if (ret != 0) {
75 debug("%s: Error while reading register %#04x\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +053076 __func__, reg);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +000077 return -1;
78 }
79
80 return 0;
81}
82
83/*
84 * update device register bits through i2c
85 *
86 * @param reg codec register
87 * @param mask register mask
88 * @param value new value
89 *
90 * @return int value 0 for success, non-zero error code.
91 */
92static int max98095_update_bits(unsigned int reg, unsigned char mask,
93 unsigned char value)
94{
95 int change, ret = 0;
96 unsigned char old, new;
97
98 if (max98095_i2c_read(reg, &old) != 0)
99 return -1;
100 new = (old & ~mask) | (value & mask);
101 change = (old != new) ? 1 : 0;
102 if (change)
103 ret = max98095_i2c_write(reg, new);
104 if (ret < 0)
105 return ret;
106
107 return change;
108}
109
110/*
111 * codec mclk clock divider coefficients based on sampling rate
112 *
113 * @param rate sampling rate
114 * @param value address of indexvalue to be stored
115 *
116 * @return 0 for success or negative error code.
117 */
118static int rate_value(int rate, u8 *value)
119{
120 int i;
121
122 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
123 if (rate_table[i] >= rate) {
124 *value = i;
125 return 0;
126 }
127 }
128 *value = 1;
129
130 return -1;
131}
132
133/*
134 * Sets hw params for max98095
135 *
136 * @param max98095 max98095 information pointer
137 * @param rate Sampling rate
138 * @param bits_per_sample Bits per sample
139 *
140 * @return -1 for error and 0 Success.
141 */
142static int max98095_hw_params(struct max98095_priv *max98095,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530143 enum en_max_audio_interface aif_id,
144 unsigned int rate, unsigned int bits_per_sample)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000145{
146 u8 regval;
147 int error;
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530148 unsigned short M98095_DAI_CLKMODE;
149 unsigned short M98095_DAI_FORMAT;
150 unsigned short M98095_DAI_FILTERS;
151
152 if (aif_id == AIF1) {
153 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
154 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
155 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
156 } else {
157 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
158 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
159 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
160 }
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000161
162 switch (bits_per_sample) {
163 case 16:
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530164 error = max98095_update_bits(M98095_DAI_FORMAT,
165 M98095_DAI_WS, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000166 break;
167 case 24:
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530168 error = max98095_update_bits(M98095_DAI_FORMAT,
169 M98095_DAI_WS, M98095_DAI_WS);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000170 break;
171 default:
172 debug("%s: Illegal bits per sample %d.\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530173 __func__, bits_per_sample);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000174 return -1;
175 }
176
177 if (rate_value(rate, &regval)) {
178 debug("%s: Failed to set sample rate to %d.\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530179 __func__, rate);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000180 return -1;
181 }
182 max98095->rate = rate;
183
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530184 error |= max98095_update_bits(M98095_DAI_CLKMODE,
185 M98095_CLKMODE_MASK, regval);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000186
187 /* Update sample rate mode */
188 if (rate < 50000)
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530189 error |= max98095_update_bits(M98095_DAI_FILTERS,
190 M98095_DAI_DHF, 0);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000191 else
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530192 error |= max98095_update_bits(M98095_DAI_FILTERS,
193 M98095_DAI_DHF, M98095_DAI_DHF);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000194
195 if (error < 0) {
196 debug("%s: Error setting hardware params.\n", __func__);
197 return -1;
198 }
199
200 return 0;
201}
202
203/*
204 * Configures Audio interface system clock for the given frequency
205 *
206 * @param max98095 max98095 information
207 * @param freq Sampling frequency in Hz
208 *
209 * @return -1 for error and 0 success.
210 */
211static int max98095_set_sysclk(struct max98095_priv *max98095,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530212 unsigned int freq)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000213{
214 int error = 0;
215
216 /* Requested clock frequency is already setup */
217 if (freq == max98095->sysclk)
218 return 0;
219
220 /* Setup clocks for slave mode, and using the PLL
221 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
222 * 0x02 (when master clk is 20MHz to 40MHz)..
223 * 0x03 (when master clk is 40MHz to 60MHz)..
224 */
225 if ((freq >= 10000000) && (freq < 20000000)) {
226 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10);
227 } else if ((freq >= 20000000) && (freq < 40000000)) {
228 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20);
229 } else if ((freq >= 40000000) && (freq < 60000000)) {
230 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30);
231 } else {
232 debug("%s: Invalid master clock frequency\n", __func__);
233 return -1;
234 }
235
236 debug("%s: Clock at %uHz\n", __func__, freq);
237
238 if (error < 0)
239 return -1;
240
241 max98095->sysclk = freq;
242 return 0;
243}
244
245/*
246 * Sets Max98095 I2S format
247 *
248 * @param max98095 max98095 information
249 * @param fmt i2S format - supports a subset of the options defined
250 * in i2s.h.
251 *
252 * @return -1 for error and 0 Success.
253 */
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530254static int max98095_set_fmt(struct max98095_priv *max98095, int fmt,
255 enum en_max_audio_interface aif_id)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000256{
257 u8 regval = 0;
258 int error = 0;
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530259 unsigned short M98095_DAI_CLKCFG_HI;
260 unsigned short M98095_DAI_CLKCFG_LO;
261 unsigned short M98095_DAI_FORMAT;
262 unsigned short M98095_DAI_CLOCK;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000263
264 if (fmt == max98095->fmt)
265 return 0;
266
267 max98095->fmt = fmt;
268
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530269 if (aif_id == AIF1) {
270 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
271 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
272 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
273 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
274 } else {
275 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
276 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
277 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
278 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
279 }
280
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000281 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
282 case SND_SOC_DAIFMT_CBS_CFS:
283 /* Slave mode PLL */
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530284 error |= max98095_i2c_write(M98095_DAI_CLKCFG_HI,
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000285 0x80);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530286 error |= max98095_i2c_write(M98095_DAI_CLKCFG_LO,
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000287 0x00);
288 break;
289 case SND_SOC_DAIFMT_CBM_CFM:
290 /* Set to master mode */
291 regval |= M98095_DAI_MAS;
292 break;
293 case SND_SOC_DAIFMT_CBS_CFM:
294 case SND_SOC_DAIFMT_CBM_CFS:
295 default:
296 debug("%s: Clock mode unsupported\n", __func__);
297 return -1;
298 }
299
300 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
301 case SND_SOC_DAIFMT_I2S:
302 regval |= M98095_DAI_DLY;
303 break;
304 case SND_SOC_DAIFMT_LEFT_J:
305 break;
306 default:
307 debug("%s: Unrecognized format.\n", __func__);
308 return -1;
309 }
310
311 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
312 case SND_SOC_DAIFMT_NB_NF:
313 break;
314 case SND_SOC_DAIFMT_NB_IF:
315 regval |= M98095_DAI_WCI;
316 break;
317 case SND_SOC_DAIFMT_IB_NF:
318 regval |= M98095_DAI_BCI;
319 break;
320 case SND_SOC_DAIFMT_IB_IF:
321 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
322 break;
323 default:
324 debug("%s: Unrecognized inversion settings.\n", __func__);
325 return -1;
326 }
327
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530328 error |= max98095_update_bits(M98095_DAI_FORMAT,
329 M98095_DAI_MAS | M98095_DAI_DLY |
330 M98095_DAI_BCI | M98095_DAI_WCI,
331 regval);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000332
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530333 error |= max98095_i2c_write(M98095_DAI_CLOCK,
334 M98095_DAI_BSEL64);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000335
336 if (error < 0) {
337 debug("%s: Error setting i2s format.\n", __func__);
338 return -1;
339 }
340
341 return 0;
342}
343
344/*
345 * resets the audio codec
346 *
347 * @return -1 for error and 0 success.
348 */
349static int max98095_reset(void)
350{
351 int i, ret;
352
353 /*
354 * Gracefully reset the DSP core and the codec hardware in a proper
355 * sequence.
356 */
357 ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0);
358 if (ret != 0) {
359 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
360 return ret;
361 }
362
363 ret = max98095_i2c_write(M98095_097_PWR_SYS, 0);
364 if (ret != 0) {
365 debug("%s: Failed to reset codec: %d\n", __func__, ret);
366 return ret;
367 }
368
369 /*
370 * Reset to hardware default for registers, as there is not a soft
371 * reset hardware control register.
372 */
373 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
374 ret = max98095_i2c_write(i, 0);
375 if (ret < 0) {
376 debug("%s: Failed to reset: %d\n", __func__, ret);
377 return ret;
378 }
379 }
380
381 return 0;
382}
383
384/*
385 * Intialise max98095 codec device
386 *
387 * @param max98095 max98095 information
388 *
389 * @returns -1 for error and 0 Success.
390 */
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530391static int max98095_device_init(struct max98095_priv *max98095,
392 enum en_max_audio_interface aif_id)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000393{
394 unsigned char id;
395 int error = 0;
396
397 /* reset the codec, the DSP core, and disable all interrupts */
398 error = max98095_reset();
399 if (error != 0) {
400 debug("Reset\n");
401 return error;
402 }
403
404 /* initialize private data */
405 max98095->sysclk = -1U;
406 max98095->rate = -1U;
407 max98095->fmt = -1U;
408
409 error = max98095_i2c_read(M98095_0FF_REV_ID, &id);
410 if (error < 0) {
411 debug("%s: Failure reading hardware revision: %d\n",
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530412 __func__, id);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000413 goto err_access;
414 }
415 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
416
417 error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV);
418
419 /*
420 * initialize registers to hardware default configuring audio
421 * interface2 to DAC
422 */
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530423 if (aif_id == AIF1)
424 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
425 M98095_DAI1L_TO_DACL |
426 M98095_DAI1R_TO_DACR);
427 else
428 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
429 M98095_DAI2M_TO_DACL |
430 M98095_DAI2M_TO_DACR);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000431
432 error |= max98095_i2c_write(M98095_092_PWR_EN_OUT,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530433 M98095_SPK_SPREADSPECTRUM);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000434 error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530435 if (aif_id == AIF1)
436 error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG,
437 M98095_S1NORMAL | M98095_SDATA);
438 else
439 error |= max98095_i2c_write(M98095_036_DAI2_IOCFG,
440 M98095_S2NORMAL | M98095_SDATA);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000441
442 /* take the codec out of the shut down */
443 error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530444 M98095_SHDNRUN);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000445 /* route DACL and DACR output to HO and Spekers */
446 error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */
447 error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */
448 error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */
449 error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */
450
451 /* power Enable */
452 error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3);
453
454 /* set Volume */
455 error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15);
456 error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15);
457 error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16);
458 error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16);
459
460 /* Enable DAIs */
461 error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530462 if (aif_id == AIF1)
463 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01);
464 else
465 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000466
467err_access:
468 if (error < 0)
469 return -1;
470
471 return 0;
472}
473
474static int max98095_do_init(struct sound_codec_info *pcodec_info,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530475 enum en_max_audio_interface aif_id,
476 int sampling_rate, int mclk_freq,
477 int bits_per_sample)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000478{
479 int ret = 0;
480
481 /* Enable codec clock */
482 set_xclkout();
483
484 /* shift the device address by 1 for 7 bit addressing */
485 g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1;
486
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530487 if (pcodec_info->codec_type == CODEC_MAX_98095) {
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000488 g_max98095_info.devtype = MAX98095;
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530489 } else {
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000490 debug("%s: Codec id [%d] not defined\n", __func__,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530491 pcodec_info->codec_type);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000492 return -1;
493 }
494
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530495 ret = max98095_device_init(&g_max98095_info, aif_id);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000496 if (ret < 0) {
497 debug("%s: max98095 codec chip init failed\n", __func__);
498 return ret;
499 }
500
501 ret = max98095_set_sysclk(&g_max98095_info, mclk_freq);
502 if (ret < 0) {
503 debug("%s: max98095 codec set sys clock failed\n", __func__);
504 return ret;
505 }
506
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530507 ret = max98095_hw_params(&g_max98095_info, aif_id, sampling_rate,
508 bits_per_sample);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000509
510 if (ret == 0) {
511 ret = max98095_set_fmt(&g_max98095_info,
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530512 SND_SOC_DAIFMT_I2S |
513 SND_SOC_DAIFMT_NB_NF |
514 SND_SOC_DAIFMT_CBS_CFS,
515 aif_id);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000516 }
517
518 return ret;
519}
520
521static int get_max98095_codec_values(struct sound_codec_info *pcodec_info,
522 const void *blob)
523{
524 int error = 0;
Masahiro Yamada0f925822015-08-12 07:31:55 +0900525#if CONFIG_IS_ENABLED(OF_CONTROL)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000526 enum fdt_compat_id compat;
527 int node;
528 int parent;
529
530 /* Get the node from FDT for codec */
531 node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC);
532 if (node <= 0) {
533 debug("EXYNOS_SOUND: No node for codec in device tree\n");
534 debug("node = %d\n", node);
535 return -1;
536 }
537
538 parent = fdt_parent_offset(blob, node);
539 if (parent < 0) {
540 debug("%s: Cannot find node parent\n", __func__);
541 return -1;
542 }
543
544 compat = fdtdec_lookup(blob, parent);
545 switch (compat) {
546 case COMPAT_SAMSUNG_S3C2440_I2C:
547 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
548 error |= pcodec_info->i2c_bus;
549 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
550 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
551 "reg", 0);
552 error |= pcodec_info->i2c_dev_addr;
553 debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr);
554 break;
555 default:
556 debug("%s: Unknown compat id %d\n", __func__, compat);
557 return -1;
558 }
559#else
560 pcodec_info->i2c_bus = AUDIO_I2C_BUS;
561 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
562 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
563#endif
564 pcodec_info->codec_type = CODEC_MAX_98095;
565 if (error == -1) {
566 debug("fail to get max98095 codec node properties\n");
567 return -1;
568 }
569
570 return 0;
571}
572
573/* max98095 Device Initialisation */
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530574int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
575 int sampling_rate, int mclk_freq,
576 int bits_per_sample)
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000577{
578 int ret;
579 int old_bus = i2c_get_bus_num();
580 struct sound_codec_info *pcodec_info = &g_codec_info;
581
582 if (get_max98095_codec_values(pcodec_info, blob) < 0) {
583 debug("FDT Codec values failed\n");
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530584 return -1;
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000585 }
586
587 i2c_set_bus_num(pcodec_info->i2c_bus);
Dani Krishna Mohan6b408522013-09-11 16:38:50 +0530588 ret = max98095_do_init(pcodec_info, aif_id, sampling_rate, mclk_freq,
589 bits_per_sample);
Rajeshwari Shinde5febe8d2013-02-14 19:46:12 +0000590 i2c_set_bus_num(old_bus);
591
592 return ret;
593}