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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Tom Warrenf29f0862013-01-23 14:01:01 -07002/*
Thierry Redingf9ec2ec2019-04-15 11:32:25 +02003 * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
Tom Warrenf29f0862013-01-23 14:01:01 -07004 */
5
6/* Tegra SoC common clock control functions */
7
8#include <common.h>
Simon Glass03bc3f12017-06-12 06:21:39 -06009#include <div64.h>
10#include <dm.h>
Simon Glass746dc762015-06-05 14:39:36 -060011#include <errno.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070012#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/tegra.h>
Stephen Warren73c38932015-01-19 16:25:52 -070015#include <asm/arch-tegra/ap.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070016#include <asm/arch-tegra/clk_rst.h>
Simon Glass746dc762015-06-05 14:39:36 -060017#include <asm/arch-tegra/pmc.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070018#include <asm/arch-tegra/timer.h>
Tom Warrenf29f0862013-01-23 14:01:01 -070019
20/*
21 * This is our record of the current clock rate of each clock. We don't
22 * fill all of these in since we are only really interested in clocks which
23 * we use as parents.
24 */
25static unsigned pll_rate[CLOCK_ID_COUNT];
26
27/*
28 * The oscillator frequency is fixed to one of four set values. Based on this
29 * the other clocks are set up appropriately.
30 */
31static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
32 13000000,
33 19200000,
34 12000000,
35 26000000,
Tom Warren3e8650c2015-06-22 13:03:44 -070036 38400000,
37 48000000,
Tom Warrenf29f0862013-01-23 14:01:01 -070038};
39
40/* return 1 if a peripheral ID is in range */
41#define clock_type_id_isvalid(id) ((id) >= 0 && \
42 (id) < CLOCK_TYPE_COUNT)
43
44char pllp_valid = 1; /* PLLP is set up correctly */
45
46/* return 1 if a periphc_internal_id is in range */
47#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
48 (id) < PERIPHC_COUNT)
49
50/* number of clock outputs of a PLL */
51static const u8 pll_num_clkouts[] = {
52 1, /* PLLC */
53 1, /* PLLM */
54 4, /* PLLP */
55 1, /* PLLA */
56 0, /* PLLU */
57 0, /* PLLD */
58};
59
60int clock_get_osc_bypass(void)
61{
62 struct clk_rst_ctlr *clkrst =
63 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
64 u32 reg;
65
66 reg = readl(&clkrst->crc_osc_ctrl);
67 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
68}
69
70/* Returns a pointer to the registers of the given pll */
71static struct clk_pll *get_pll(enum clock_id clkid)
72{
73 struct clk_rst_ctlr *clkrst =
74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
75
76 assert(clock_id_is_pll(clkid));
Simon Glass801b05c2015-04-14 21:03:32 -060077 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
Simon Glasscd3c6762015-06-05 14:39:37 -060078 debug("%s: Invalid PLL %d\n", __func__, clkid);
Simon Glass801b05c2015-04-14 21:03:32 -060079 return NULL;
80 }
Tom Warrenf29f0862013-01-23 14:01:01 -070081 return &clkrst->crc_pll[clkid];
82}
83
Simon Glass801b05c2015-04-14 21:03:32 -060084__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
85{
86 return NULL;
87}
88
Tom Warrenf29f0862013-01-23 14:01:01 -070089int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
90 u32 *divp, u32 *cpcon, u32 *lfcon)
91{
92 struct clk_pll *pll = get_pll(clkid);
Tom Warren722e0002015-06-25 09:50:44 -070093 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warrenf29f0862013-01-23 14:01:01 -070094 u32 data;
95
96 assert(clkid != CLOCK_ID_USB);
97
98 /* Safety check, adds to code size but is small */
99 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
100 return -1;
101 data = readl(&pll->pll_base);
Tom Warren722e0002015-06-25 09:50:44 -0700102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
103 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
104 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
Tom Warrenf29f0862013-01-23 14:01:01 -0700105 data = readl(&pll->pll_misc);
Tom Warren722e0002015-06-25 09:50:44 -0700106 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
107 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
108 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
109
Tom Warrenf29f0862013-01-23 14:01:01 -0700110 return 0;
111}
112
113unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
114 u32 divp, u32 cpcon, u32 lfcon)
115{
Simon Glasscd3c6762015-06-05 14:39:37 -0600116 struct clk_pll *pll = NULL;
Tom Warren722e0002015-06-25 09:50:44 -0700117 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Simon Glass5a30cee2015-08-10 07:14:36 -0600118 struct clk_pll_simple *simple_pll = NULL;
Simon Glass801b05c2015-04-14 21:03:32 -0600119 u32 misc_data, data;
Tom Warrenf29f0862013-01-23 14:01:01 -0700120
Simon Glass5a30cee2015-08-10 07:14:36 -0600121 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
Simon Glasscd3c6762015-06-05 14:39:37 -0600122 pll = get_pll(clkid);
Simon Glass5a30cee2015-08-10 07:14:36 -0600123 } else {
124 simple_pll = clock_get_simple_pll(clkid);
125 if (!simple_pll) {
126 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
127 return 0;
128 }
129 }
Simon Glasscd3c6762015-06-05 14:39:37 -0600130
Tom Warrenf29f0862013-01-23 14:01:01 -0700131 /*
Tom Warren722e0002015-06-25 09:50:44 -0700132 * pllinfo has the m/n/p and kcp/kvco mask and shift
133 * values for all of the PLLs used in U-Boot, with any
134 * SoC differences accounted for.
Simon Glass5a30cee2015-08-10 07:14:36 -0600135 *
136 * Preserve EN_LOCKDET, etc.
Tom Warrenf29f0862013-01-23 14:01:01 -0700137 */
Simon Glass5a30cee2015-08-10 07:14:36 -0600138 if (pll)
139 misc_data = readl(&pll->pll_misc);
140 else
141 misc_data = readl(&simple_pll->pll_misc);
142 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
143 misc_data |= cpcon << pllinfo->kcp_shift;
144 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
145 misc_data |= lfcon << pllinfo->kvco_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700146
Tom Warren722e0002015-06-25 09:50:44 -0700147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
148 data |= divp << pllinfo->p_shift;
149 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
Tom Warrenf29f0862013-01-23 14:01:01 -0700150
Simon Glass801b05c2015-04-14 21:03:32 -0600151 if (pll) {
152 writel(misc_data, &pll->pll_misc);
153 writel(data, &pll->pll_base);
154 } else {
Simon Glass5a30cee2015-08-10 07:14:36 -0600155 writel(misc_data, &simple_pll->pll_misc);
156 writel(data, &simple_pll->pll_base);
Simon Glass801b05c2015-04-14 21:03:32 -0600157 }
Tom Warrenf29f0862013-01-23 14:01:01 -0700158
159 /* calculate the stable time */
160 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
161}
162
163void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
164 unsigned divisor)
165{
166 u32 *reg = get_periph_source_reg(periph_id);
167 u32 value;
168
169 value = readl(reg);
170
Stephen Warren9cb0c6d2014-01-24 10:16:19 -0700171 value &= ~OUT_CLK_SOURCE_31_30_MASK;
172 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
Tom Warrenf29f0862013-01-23 14:01:01 -0700173
174 value &= ~OUT_CLK_DIVISOR_MASK;
175 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
176
177 writel(value, reg);
178}
179
Simon Glass7bb61992015-04-14 21:03:33 -0600180int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
181 unsigned source)
Tom Warrenf29f0862013-01-23 14:01:01 -0700182{
183 u32 *reg = get_periph_source_reg(periph_id);
184
Simon Glass7bb61992015-04-14 21:03:33 -0600185 switch (mux_bits) {
186 case MASK_BITS_31_30:
187 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
188 source << OUT_CLK_SOURCE_31_30_SHIFT);
189 break;
190
191 case MASK_BITS_31_29:
192 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
193 source << OUT_CLK_SOURCE_31_29_SHIFT);
194 break;
195
196 case MASK_BITS_31_28:
197 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
198 source << OUT_CLK_SOURCE_31_28_SHIFT);
199 break;
200
201 default:
202 return -1;
203 }
204
205 return 0;
206}
207
Stephen Warrend0ad8a52016-09-13 10:45:56 -0600208static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
209{
210 u32 *reg = get_periph_source_reg(periph_id);
211 u32 val = readl(reg);
212
213 switch (mux_bits) {
214 case MASK_BITS_31_30:
215 val >>= OUT_CLK_SOURCE_31_30_SHIFT;
216 val &= OUT_CLK_SOURCE_31_30_MASK;
217 return val;
218 case MASK_BITS_31_29:
219 val >>= OUT_CLK_SOURCE_31_29_SHIFT;
220 val &= OUT_CLK_SOURCE_31_29_MASK;
221 return val;
222 case MASK_BITS_31_28:
223 val >>= OUT_CLK_SOURCE_31_28_SHIFT;
224 val &= OUT_CLK_SOURCE_31_28_MASK;
225 return val;
226 default:
227 return -1;
228 }
229}
230
Simon Glass7bb61992015-04-14 21:03:33 -0600231void clock_ll_set_source(enum periph_id periph_id, unsigned source)
232{
233 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
Tom Warrenf29f0862013-01-23 14:01:01 -0700234}
235
236/**
237 * Given the parent's rate and the required rate for the children, this works
238 * out the peripheral clock divider to use, in 7.1 binary format.
239 *
240 * @param divider_bits number of divider bits (8 or 16)
241 * @param parent_rate clock rate of parent clock in Hz
242 * @param rate required clock rate for this clock
243 * @return divider which should be used
244 */
245static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
246 unsigned long rate)
247{
248 u64 divider = parent_rate * 2;
249 unsigned max_divider = 1 << divider_bits;
250
251 divider += rate - 1;
252 do_div(divider, rate);
253
254 if ((s64)divider - 2 < 0)
255 return 0;
256
257 if ((s64)divider - 2 >= max_divider)
258 return -1;
259
260 return divider - 2;
261}
262
263int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
264{
265 struct clk_pll *pll = get_pll(clkid);
266 int data = 0, div = 0, offset = 0;
267
268 if (!clock_id_is_pll(clkid))
269 return -1;
270
271 if (pllout + 1 > pll_num_clkouts[clkid])
272 return -1;
273
274 div = clk_get_divider(8, pll_rate[clkid], rate);
275
276 if (div < 0)
277 return -1;
278
279 /* out2 and out4 are in the high part of the register */
280 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
281 offset = 16;
282
283 data = (div << PLL_OUT_RATIO_SHIFT) |
284 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
285 clrsetbits_le32(&pll->pll_out[pllout >> 1],
286 PLL_OUT_RATIO_MASK << offset, data << offset);
287
288 return 0;
289}
290
291/**
292 * Given the parent's rate and the divider in 7.1 format, this works out the
293 * resulting peripheral clock rate.
294 *
295 * @param parent_rate clock rate of parent clock in Hz
296 * @param divider which should be used in 7.1 format
297 * @return effective clock rate of peripheral
298 */
299static unsigned long get_rate_from_divider(unsigned long parent_rate,
300 int divider)
301{
302 u64 rate;
303
304 rate = (u64)parent_rate * 2;
305 do_div(rate, divider + 2);
306 return rate;
307}
308
309unsigned long clock_get_periph_rate(enum periph_id periph_id,
310 enum clock_id parent)
311{
312 u32 *reg = get_periph_source_reg(periph_id);
Stephen Warren74686762016-09-23 16:44:51 -0600313 unsigned parent_rate = pll_rate[parent];
314 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
Tom Warrenf29f0862013-01-23 14:01:01 -0700315
Stephen Warren74686762016-09-23 16:44:51 -0600316 switch (periph_id) {
317 case PERIPH_ID_UART1:
318 case PERIPH_ID_UART2:
319 case PERIPH_ID_UART3:
320 case PERIPH_ID_UART4:
321 case PERIPH_ID_UART5:
322#ifdef CONFIG_TEGRA20
323 /* There's no divider for these clocks in this SoC. */
324 return parent_rate;
325#else
326 /*
327 * This undoes the +2 in get_rate_from_divider() which I
328 * believe is incorrect. Ideally we would fix
329 * get_rate_from_divider(), but... Removing the +2 from
330 * get_rate_from_divider() would probably require remove the -2
331 * from the tail of clk_get_divider() since I believe that's
332 * only there to invert get_rate_from_divider()'s +2. Observe
333 * how find_best_divider() uses those two functions together.
334 * However, doing so breaks other stuff, such as Seaboard's
335 * display, likely due to clock_set_pllout()'s call to
336 * clk_get_divider(). Attempting to fix that by making
337 * clock_set_pllout() subtract 2 from clk_get_divider()'s
338 * return value doesn't help. In summary this clock driver is
339 * quite broken but I'm afraid I have no idea how to fix it
340 * without completely replacing it.
Simon Glass1c6c7b62017-05-31 17:57:22 -0600341 *
342 * Be careful to avoid a divide by zero error.
Stephen Warren74686762016-09-23 16:44:51 -0600343 */
Simon Glass1c6c7b62017-05-31 17:57:22 -0600344 if (div >= 1)
345 div -= 2;
Stephen Warren74686762016-09-23 16:44:51 -0600346 break;
347#endif
348 default:
349 break;
350 }
351
352 return get_rate_from_divider(parent_rate, div);
Tom Warrenf29f0862013-01-23 14:01:01 -0700353}
354
355/**
356 * Find the best available 7.1 format divisor given a parent clock rate and
357 * required child clock rate. This function assumes that a second-stage
358 * divisor is available which can divide by powers of 2 from 1 to 256.
359 *
360 * @param divider_bits number of divider bits (8 or 16)
361 * @param parent_rate clock rate of parent clock in Hz
362 * @param rate required clock rate for this clock
363 * @param extra_div value for the second-stage divisor (not set if this
364 * function returns -1.
365 * @return divider which should be used, or -1 if nothing is valid
366 *
367 */
368static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
369 unsigned long rate, int *extra_div)
370{
371 int shift;
372 int best_divider = -1;
373 int best_error = rate;
374
375 /* try dividers from 1 to 256 and find closest match */
376 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
377 unsigned divided_parent = parent_rate >> shift;
378 int divider = clk_get_divider(divider_bits, divided_parent,
379 rate);
380 unsigned effective_rate = get_rate_from_divider(divided_parent,
381 divider);
382 int error = rate - effective_rate;
383
384 /* Given a valid divider, look for the lowest error */
385 if (divider != -1 && error < best_error) {
386 best_error = error;
387 *extra_div = 1 << shift;
388 best_divider = divider;
389 }
390 }
391
392 /* return what we found - *extra_div will already be set */
393 return best_divider;
394}
395
396/**
397 * Adjust peripheral PLL to use the given divider and source.
398 *
399 * @param periph_id peripheral to adjust
400 * @param source Source number (0-3 or 0-7)
401 * @param mux_bits Number of mux bits (2 or 4)
402 * @param divider Required divider in 7.1 or 15.1 format
403 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
404 * for this peripheral)
405 */
406static int adjust_periph_pll(enum periph_id periph_id, int source,
407 int mux_bits, unsigned divider)
408{
409 u32 *reg = get_periph_source_reg(periph_id);
410
411 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
412 divider << OUT_CLK_DIVISOR_SHIFT);
413 udelay(1);
414
415 /* work out the source clock and set it */
416 if (source < 0)
417 return -1;
Tom Warrenc82014d2014-01-24 10:16:22 -0700418
Simon Glass7bb61992015-04-14 21:03:33 -0600419 clock_ll_set_source_bits(periph_id, mux_bits, source);
Tom Warrenc82014d2014-01-24 10:16:22 -0700420
Tom Warrenf29f0862013-01-23 14:01:01 -0700421 udelay(2);
422 return 0;
423}
424
Stephen Warrend0ad8a52016-09-13 10:45:56 -0600425enum clock_id clock_get_periph_parent(enum periph_id periph_id)
426{
427 int err, mux_bits, divider_bits, type;
428 int source;
429
430 err = get_periph_clock_info(periph_id, &mux_bits, &divider_bits, &type);
431 if (err)
432 return CLOCK_ID_NONE;
433
434 source = clock_ll_get_source_bits(periph_id, mux_bits);
435
436 return get_periph_clock_id(periph_id, source);
437}
438
Tom Warrenf29f0862013-01-23 14:01:01 -0700439unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
440 enum clock_id parent, unsigned rate, int *extra_div)
441{
442 unsigned effective_rate;
443 int mux_bits, divider_bits, source;
444 int divider;
Allen Martina51f7de2013-05-10 16:56:55 +0000445 int xdiv = 0;
Tom Warrenf29f0862013-01-23 14:01:01 -0700446
447 /* work out the source clock and set it */
448 source = get_periph_clock_source(periph_id, parent, &mux_bits,
449 &divider_bits);
450
Allen Martina51f7de2013-05-10 16:56:55 +0000451 divider = find_best_divider(divider_bits, pll_rate[parent],
452 rate, &xdiv);
Tom Warrenf29f0862013-01-23 14:01:01 -0700453 if (extra_div)
Allen Martina51f7de2013-05-10 16:56:55 +0000454 *extra_div = xdiv;
455
Tom Warrenf29f0862013-01-23 14:01:01 -0700456 assert(divider >= 0);
457 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
458 return -1U;
459 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
460 get_periph_source_reg(periph_id),
461 readl(get_periph_source_reg(periph_id)));
462
463 /* Check what we ended up with. This shouldn't matter though */
464 effective_rate = clock_get_periph_rate(periph_id, parent);
465 if (extra_div)
466 effective_rate /= *extra_div;
467 if (rate != effective_rate)
468 debug("Requested clock rate %u not honored (got %u)\n",
469 rate, effective_rate);
470 return effective_rate;
471}
472
473unsigned clock_start_periph_pll(enum periph_id periph_id,
474 enum clock_id parent, unsigned rate)
475{
476 unsigned effective_rate;
477
478 reset_set_enable(periph_id, 1);
479 clock_enable(periph_id);
Simon Glassc9d75422019-04-01 13:38:38 -0700480 udelay(2);
Tom Warrenf29f0862013-01-23 14:01:01 -0700481
482 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
483 NULL);
484
485 reset_set_enable(periph_id, 0);
486 return effective_rate;
487}
488
489void clock_enable(enum periph_id clkid)
490{
491 clock_set_enable(clkid, 1);
492}
493
494void clock_disable(enum periph_id clkid)
495{
496 clock_set_enable(clkid, 0);
497}
498
499void reset_periph(enum periph_id periph_id, int us_delay)
500{
501 /* Put peripheral into reset */
502 reset_set_enable(periph_id, 1);
503 udelay(us_delay);
504
505 /* Remove reset */
506 reset_set_enable(periph_id, 0);
507
508 udelay(us_delay);
509}
510
511void reset_cmplx_set_enable(int cpu, int which, int reset)
512{
513 struct clk_rst_ctlr *clkrst =
514 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
515 u32 mask;
516
517 /* Form the mask, which depends on the cpu chosen (2 or 4) */
518 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
519 mask = which << cpu;
520
521 /* either enable or disable those reset for that CPU */
522 if (reset)
523 writel(mask, &clkrst->crc_cpu_cmplx_set);
524 else
525 writel(mask, &clkrst->crc_cpu_cmplx_clr);
526}
527
Thierry Redingc043c022015-08-20 11:42:19 +0200528unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
529{
530 return parent_rate;
531}
532
Tom Warrenf29f0862013-01-23 14:01:01 -0700533unsigned clock_get_rate(enum clock_id clkid)
534{
535 struct clk_pll *pll;
Tom Warren722e0002015-06-25 09:50:44 -0700536 u32 base, divm;
537 u64 parent_rate, rate;
538 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warrenf29f0862013-01-23 14:01:01 -0700539
540 parent_rate = osc_freq[clock_get_osc_freq()];
541 if (clkid == CLOCK_ID_OSC)
542 return parent_rate;
543
Thierry Redingc043c022015-08-20 11:42:19 +0200544 if (clkid == CLOCK_ID_CLK_M)
545 return clk_m_get_rate(parent_rate);
546
Tom Warrenf29f0862013-01-23 14:01:01 -0700547 pll = get_pll(clkid);
Simon Glass801b05c2015-04-14 21:03:32 -0600548 if (!pll)
549 return 0;
Tom Warrenf29f0862013-01-23 14:01:01 -0700550 base = readl(&pll->pll_base);
551
Tom Warren722e0002015-06-25 09:50:44 -0700552 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
553 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
554 /*
555 * PLLU uses p_mask/p_shift for VCO on all but T210,
556 * T210 uses normal DIVP. Handled in pllinfo table.
557 */
Stephen Warren6c7dc622015-08-19 17:03:59 -0600558#ifdef CONFIG_TEGRA210
559 /*
560 * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
561 * not applied. pllP_out2 does have divp applied. All other pllP_outN
562 * are divided down from pllP_out0. We only support pllP_out0 in
563 * U-Boot at the time of writing this comment.
564 */
565 if (clkid != CLOCK_ID_PERIPH)
566#endif
567 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
Tom Warrenf29f0862013-01-23 14:01:01 -0700568 do_div(rate, divm);
569 return rate;
570}
571
572/**
573 * Set the output frequency you want for each PLL clock.
574 * PLL output frequencies are programmed by setting their N, M and P values.
575 * The governing equations are:
576 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
577 * where Fo is the output frequency from the PLL.
578 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
579 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
580 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
581 *
582 * @param n PLL feedback divider(DIVN)
583 * @param m PLL input divider(DIVN)
584 * @param p post divider(DIVP)
585 * @param cpcon base PLL charge pump(CPCON)
586 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
Robert P. J. Day62a3b7d2016-07-15 13:44:45 -0400587 * be overridden), 1 if PLL is already correct
Tom Warrenf29f0862013-01-23 14:01:01 -0700588 */
589int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
590{
Tom Warren722e0002015-06-25 09:50:44 -0700591 u32 base_reg, misc_reg;
Tom Warrenf29f0862013-01-23 14:01:01 -0700592 struct clk_pll *pll;
Tom Warren722e0002015-06-25 09:50:44 -0700593 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
Tom Warrenf29f0862013-01-23 14:01:01 -0700594
595 pll = get_pll(clkid);
596
597 base_reg = readl(&pll->pll_base);
598
599 /* Set BYPASS, m, n and p to PLL_BASE */
Tom Warren722e0002015-06-25 09:50:44 -0700600 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
601 base_reg |= m << pllinfo->m_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700602
Tom Warren722e0002015-06-25 09:50:44 -0700603 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
604 base_reg |= n << pllinfo->n_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700605
Tom Warren722e0002015-06-25 09:50:44 -0700606 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
607 base_reg |= p << pllinfo->p_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700608
609 if (clkid == CLOCK_ID_PERIPH) {
610 /*
611 * If the PLL is already set up, check that it is correct
612 * and record this info for clock_verify() to check.
613 */
614 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
615 base_reg |= PLL_ENABLE_MASK;
616 if (base_reg != readl(&pll->pll_base))
617 pllp_valid = 0;
618 return pllp_valid ? 1 : -1;
619 }
620 base_reg |= PLL_BASE_OVRRIDE_MASK;
621 }
622
623 base_reg |= PLL_BYPASS_MASK;
624 writel(base_reg, &pll->pll_base);
625
Tom Warren722e0002015-06-25 09:50:44 -0700626 /* Set cpcon (KCP) to PLL_MISC */
Tom Warrenf29f0862013-01-23 14:01:01 -0700627 misc_reg = readl(&pll->pll_misc);
Tom Warren722e0002015-06-25 09:50:44 -0700628 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
629 misc_reg |= cpcon << pllinfo->kcp_shift;
Tom Warrenf29f0862013-01-23 14:01:01 -0700630 writel(misc_reg, &pll->pll_misc);
631
632 /* Enable PLL */
633 base_reg |= PLL_ENABLE_MASK;
634 writel(base_reg, &pll->pll_base);
635
636 /* Disable BYPASS */
637 base_reg &= ~PLL_BYPASS_MASK;
638 writel(base_reg, &pll->pll_base);
639
640 return 0;
641}
642
643void clock_ll_start_uart(enum periph_id periph_id)
644{
645 /* Assert UART reset and enable clock */
646 reset_set_enable(periph_id, 1);
647 clock_enable(periph_id);
648 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
649
650 /* wait for 2us */
651 udelay(2);
652
653 /* De-assert reset to UART */
654 reset_set_enable(periph_id, 0);
655}
656
Masahiro Yamada0f925822015-08-12 07:31:55 +0900657#if CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glass000f15f2017-07-25 08:30:00 -0600658int clock_decode_periph_id(struct udevice *dev)
Tom Warrenf29f0862013-01-23 14:01:01 -0700659{
660 enum periph_id id;
661 u32 cell[2];
662 int err;
663
Simon Glass000f15f2017-07-25 08:30:00 -0600664 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
Tom Warrenf29f0862013-01-23 14:01:01 -0700665 if (err)
666 return -1;
667 id = clk_id_to_periph_id(cell[1]);
668 assert(clock_periph_id_isvalid(id));
669 return id;
670}
Masahiro Yamada0f925822015-08-12 07:31:55 +0900671#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
Tom Warrenf29f0862013-01-23 14:01:01 -0700672
673int clock_verify(void)
674{
675 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
676 u32 reg = readl(&pll->pll_base);
677
678 if (!pllp_valid) {
679 printf("Warning: PLLP %x is not correct\n", reg);
680 return -1;
681 }
682 debug("PLLP %x is correct\n", reg);
683 return 0;
684}
685
686void clock_init(void)
687{
Stephen Warren6dbcc962016-09-13 10:45:55 -0600688 int i;
689
Tom Warren3e8650c2015-06-22 13:03:44 -0700690 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
Tom Warrenf29f0862013-01-23 14:01:01 -0700691 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
692 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
Tom Warren3e8650c2015-06-22 13:03:44 -0700693 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
Simon Glass96e82a22015-04-14 21:03:34 -0600694 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
Tom Warrenf29f0862013-01-23 14:01:01 -0700695 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
Tom Warren3e8650c2015-06-22 13:03:44 -0700696 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
697 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
Thierry Redingc043c022015-08-20 11:42:19 +0200698 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
Tom Warren3e8650c2015-06-22 13:03:44 -0700699
Tom Warrenf29f0862013-01-23 14:01:01 -0700700 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
Thierry Redingc043c022015-08-20 11:42:19 +0200701 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
Tom Warren3e8650c2015-06-22 13:03:44 -0700702 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
Tom Warrenf29f0862013-01-23 14:01:01 -0700703 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
704 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
Tom Warren3e8650c2015-06-22 13:03:44 -0700705 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
Simon Glass96e82a22015-04-14 21:03:34 -0600706 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
Tom Warrenf29f0862013-01-23 14:01:01 -0700707 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
Stephen Warren6dbcc962016-09-13 10:45:55 -0600708
709 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
710 enum periph_id periph_id;
711 enum clock_id parent;
712 int source, mux_bits, divider_bits;
713
714 periph_id = periph_clk_init_table[i].periph_id;
715 parent = periph_clk_init_table[i].parent_clock_id;
716
717 source = get_periph_clock_source(periph_id, parent, &mux_bits,
718 &divider_bits);
719 clock_ll_set_source_bits(periph_id, mux_bits, source);
720 }
Tom Warrenf29f0862013-01-23 14:01:01 -0700721}
Jimmy Zhangb9dd6212014-01-24 10:37:36 -0700722
723static void set_avp_clock_source(u32 src)
724{
725 struct clk_rst_ctlr *clkrst =
726 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
727 u32 val;
728
729 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
730 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
731 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
732 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
733 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
734 writel(val, &clkrst->crc_sclk_brst_pol);
735 udelay(3);
736}
737
738/*
739 * This function is useful on Tegra30, and any later SoCs that have compatible
740 * PLLP configuration registers.
Tom Warren7aaa5a62015-03-04 16:36:00 -0700741 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
Jimmy Zhangb9dd6212014-01-24 10:37:36 -0700742 */
743void tegra30_set_up_pllp(void)
744{
745 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
746 u32 reg;
747
748 /*
749 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
750 * run up to 275MHz. On power on, the default sytem clock source is set
751 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
752 * 408MHz which is beyond system clock's upper limit.
753 *
754 * The fix is to set the system clock to CLK_M before initializing PLLP,
755 * and then switch back to PLLP_OUT4, which has an appropriate divider
756 * configured, after PLLP has been configured
757 */
758 set_avp_clock_source(SCLK_SOURCE_CLKM);
759
760 /*
761 * PLLP output frequency set to 408Mhz
762 * PLLC output frequency set to 228Mhz
763 */
764 switch (clock_get_osc_freq()) {
765 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
766 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
767 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
768 break;
769
770 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
771 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
772 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
773 break;
774
775 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
776 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
777 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
778 break;
779 case CLOCK_OSC_FREQ_19_2:
780 default:
781 /*
782 * These are not supported. It is too early to print a
783 * message and the UART likely won't work anyway due to the
784 * oscillator being wrong.
785 */
786 break;
787 }
788
789 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
790
791 /* OUT1, 2 */
792 /* Assert RSTN before enable */
793 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
794 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
795 /* Set divisor and reenable */
796 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
797 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
798 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
799 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
800 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
801
802 /* OUT3, 4 */
803 /* Assert RSTN before enable */
804 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
805 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
806 /* Set divisor and reenable */
807 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
808 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
809 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
810 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
811 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
812
813 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
814}
Simon Glass746dc762015-06-05 14:39:36 -0600815
816int clock_external_output(int clk_id)
817{
Thierry Redingf9ec2ec2019-04-15 11:32:25 +0200818 u32 val;
Simon Glass746dc762015-06-05 14:39:36 -0600819
820 if (clk_id >= 1 && clk_id <= 3) {
Thierry Redingf9ec2ec2019-04-15 11:32:25 +0200821 val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
822 pmc_clk_out_cntrl));
823 val |= 1 << (2 + (clk_id - 1) * 8);
824 tegra_pmc_writel(val,
825 offsetof(struct pmc_ctlr,
826 pmc_clk_out_cntrl));
827
Simon Glass746dc762015-06-05 14:39:36 -0600828 } else {
829 printf("%s: Unknown output clock id %d\n", __func__, clk_id);
830 return -EINVAL;
831 }
832
833 return 0;
834}
Simon Glass46864cc2017-05-31 17:57:16 -0600835
836__weak bool clock_early_init_done(void)
837{
838 return true;
839}