| Masahiro Yamada | 15607d0 | 2016-01-09 01:51:14 +0900 | [diff] [blame^] | 1 | /* |
| 2 | * UniPhier DDR MultiPHY registers |
| 3 | * |
| 4 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef ARCH_DDRMPHY_REGS_H |
| 10 | #define ARCH_DDRMPHY_REGS_H |
| 11 | |
| 12 | #include <linux/bitops.h> |
| 13 | |
| 14 | #define DMPHY_SHIFT 2 |
| 15 | |
| 16 | #define DMPHY_RIDR (0x000 << DMPHY_SHIFT) |
| 17 | #define DMPHY_PIR (0x001 << DMPHY_SHIFT) |
| 18 | #define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */ |
| 19 | #define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */ |
| 20 | #define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */ |
| 21 | #define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */ |
| 22 | #define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */ |
| 23 | #define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */ |
| 24 | #define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */ |
| 25 | #define DMPHY_PIR_WL BIT(9) /* Write Leveling */ |
| 26 | #define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */ |
| 27 | #define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */ |
| 28 | #define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */ |
| 29 | #define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */ |
| 30 | #define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */ |
| 31 | #define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */ |
| 32 | #define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */ |
| 33 | #define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */ |
| 34 | #define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT) |
| 35 | #define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */ |
| 36 | #define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT) |
| 37 | #define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */ |
| 38 | #define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT) |
| 39 | #define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/ |
| 40 | #define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/ |
| 41 | #define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT) |
| 42 | #define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT) |
| 43 | #define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */ |
| 44 | #define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */ |
| 45 | #define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */ |
| 46 | #define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */ |
| 47 | #define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */ |
| 48 | #define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */ |
| 49 | #define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */ |
| 50 | #define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */ |
| 51 | #define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */ |
| 52 | #define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */ |
| 53 | #define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */ |
| 54 | #define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */ |
| 55 | #define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */ |
| 56 | #define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */ |
| 57 | #define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */ |
| 58 | #define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */ |
| 59 | #define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */ |
| 60 | #define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */ |
| 61 | #define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */ |
| 62 | #define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */ |
| 63 | #define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT) |
| 64 | #define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */ |
| 65 | #define DMPHY_PLLCR (0x008 << DMPHY_SHIFT) |
| 66 | #define DMPHY_PTR0 (0x009 << DMPHY_SHIFT) |
| 67 | #define DMPHY_PTR1 (0x00A << DMPHY_SHIFT) |
| 68 | #define DMPHY_PTR2 (0x00B << DMPHY_SHIFT) |
| 69 | #define DMPHY_PTR3 (0x00C << DMPHY_SHIFT) |
| 70 | #define DMPHY_PTR4 (0x00D << DMPHY_SHIFT) |
| 71 | #define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT) |
| 72 | #define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT) |
| 73 | #define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT) |
| 74 | #define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT) |
| 75 | #define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT) |
| 76 | #define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT) |
| 77 | #define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT) |
| 78 | #define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT) |
| 79 | #define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT) |
| 80 | #define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT) |
| 81 | #define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT) |
| 82 | #define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT) |
| 83 | #define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT) |
| 84 | #define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT) |
| 85 | #define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT) |
| 86 | #define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT) |
| 87 | #define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT) |
| 88 | #define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT) |
| 89 | #define DMPHY_DXCCR (0x020 << DMPHY_SHIFT) |
| 90 | #define DMPHY_DSGCR (0x021 << DMPHY_SHIFT) |
| 91 | #define DMPHY_DCR (0x022 << DMPHY_SHIFT) |
| 92 | #define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT) |
| 93 | #define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT) |
| 94 | #define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT) |
| 95 | #define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT) |
| 96 | #define DMPHY_MR0 (0x027 << DMPHY_SHIFT) |
| 97 | #define DMPHY_MR1 (0x028 << DMPHY_SHIFT) |
| 98 | #define DMPHY_MR2 (0x029 << DMPHY_SHIFT) |
| 99 | #define DMPHY_MR3 (0x02A << DMPHY_SHIFT) |
| 100 | #define DMPHY_ODTCR (0x02B << DMPHY_SHIFT) |
| 101 | #define DMPHY_DTCR (0x02C << DMPHY_SHIFT) |
| 102 | #define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */ |
| 103 | #define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT)) |
| 104 | #define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT) |
| 105 | #define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT) |
| 106 | #define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT) |
| 107 | #define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT) |
| 108 | #define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT) |
| 109 | #define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT) |
| 110 | #define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT) |
| 111 | #define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT) |
| 112 | #define DMPHY_ZQCR (0x090 << DMPHY_SHIFT) |
| 113 | #define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */ |
| 114 | #define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */ |
| 115 | /* ZQ */ |
| 116 | #define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT) |
| 117 | #define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT) |
| 118 | #define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT) |
| 119 | #define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT) |
| 120 | #define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT) |
| 121 | /* DATX8 */ |
| 122 | #define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT) |
| 123 | #define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT) |
| 124 | #define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT) |
| 125 | #define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ |
| 126 | #define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT)) |
| 127 | #define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT) |
| 128 | #define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT) |
| 129 | #define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT) |
| 130 | #define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT) |
| 131 | #define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT) |
| 132 | #define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT) |
| 133 | #define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT) |
| 134 | #define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT) |
| 135 | #define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT) |
| 136 | #define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT) |
| 137 | #define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT) |
| 138 | #define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT) |
| 139 | #define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT) |
| 140 | #define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT) |
| 141 | #define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT) |
| 142 | #define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT) |
| 143 | #define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT) |
| 144 | #define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT) |
| 145 | |
| 146 | #endif /* ARCH_DDRMPHY_REGS_H */ |