blob: ef9335c523f48586e0b6d5f35326f3be51f6b69e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop0176d432008-03-26 18:52:33 +01002/*
3 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Stelian Pop0176d432008-03-26 18:52:33 +01005 * Lead Tech Design <www.leadtechdesign.com>
6 *
Nicolas Ferredf486b12009-03-22 14:48:16 +01007 * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
Stelian Pop0176d432008-03-26 18:52:33 +01008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000013/*
14 * SoC must be defined first, before hardware.h is included.
15 * In this case SoC is defined in boards.cfg.
16 */
17#include <asm/hardware.h>
Stelian Pop0176d432008-03-26 18:52:33 +010018
19/*
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000020 * Warning: changing CONFIG_SYS_TEXT_BASE requires
21 * adapting the initial boot program.
22 * Since the linker has to swallow that define, we must use a pure
23 * hex number here!
Stelian Pop0176d432008-03-26 18:52:33 +010024 */
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000025
26/* ARM asynchronous clock */
27#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
28#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000029
Stelian Pop0176d432008-03-26 18:52:33 +010030/*
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000031 * SDRAM: 1 bank, min 32, max 128 MB
32 * Initialized before u-boot gets started.
33 */
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000034#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
35#define CONFIG_SYS_SDRAM_SIZE 0x04000000
36
Tom Rinieaf6ea62022-05-25 12:16:03 -040037#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000038#ifdef CONFIG_AT91SAM9XE
Tom Rinieaf6ea62022-05-25 12:16:03 -040039# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000040#else
Tom Rinieaf6ea62022-05-25 12:16:03 -040041# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000042#endif
Stelian Pop0176d432008-03-26 18:52:33 +010043
Stelian Pop0176d432008-03-26 18:52:33 +010044/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010045#ifdef CONFIG_CMD_NAND
Reinhard Meyer8c6407f2011-06-06 00:13:10 +000046#define CONFIG_SYS_MAX_NAND_DEVICE 1
47#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
48#define CONFIG_SYS_NAND_DBW_8
49#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
50#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
51#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
52#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010053#endif
Stelian Pop0176d432008-03-26 18:52:33 +010054
Stelian Pop0176d432008-03-26 18:52:33 +010055/* USB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
Stelian Pop0176d432008-03-26 18:52:33 +010057
Stelian Pop0176d432008-03-26 18:52:33 +010058#endif