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Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +02001// SPDX-License-Identifier: GPL-2.0
Stefan Roesebf2150b2016-10-25 10:10:32 +02002/*
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +02003 * Copyright (C) 2016 - 2021 Marvell International Ltd.
Stefan Roesebf2150b2016-10-25 10:10:32 +02004 */
5
6/*
7 * Device Tree file for Marvell Armada 8040 Development board platform
8 */
9
10#include "armada-8040.dtsi"
11
12/ {
13 model = "Marvell Armada 8040 DB board";
14 compatible = "marvell,armada8040-db", "marvell,armada8040",
15 "marvell,armada-ap806-quad", "marvell,armada-ap806";
16
17 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
Stefan Roeseaf4c2712016-10-25 18:11:44 +020021 aliases {
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020022 i2c0 = &cp0_i2c0;
23 spi0 = &cp1_spi1;
Stefan Roeseaf4c2712016-10-25 18:11:44 +020024 };
25
Stefan Roesebf2150b2016-10-25 10:10:32 +020026 memory@00000000 {
27 device_type = "memory";
28 reg = <0x0 0x0 0x0 0x80000000>;
29 };
30};
31
Stefan Roesebf2150b2016-10-25 10:10:32 +020032/* Accessible over the mini-USB CON9 connector on the main board */
33&uart0 {
34 status = "okay";
35};
36
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +020037&ap_pinctl {
38 /* MPP Bus:
39 * SDIO [0-10]
40 * UART0 [11,19]
41 */
42 /* 0 1 2 3 4 5 6 7 8 9 */
43 pin-func = < 1 1 1 1 1 1 1 1 1 1
44 1 3 0 0 0 0 0 0 0 3 >;
45};
46
Konstantin Porotchkin61dccf72018-05-25 14:20:53 +080047&ap_sdhci0 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&ap_emmc_pins>;
50 bus-width = <8>;
51 status = "okay";
52};
53
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020054&cp0_pinctl {
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +020055 /* MPP Bus:
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030056 * [0-31] = 0xff: Keep default CP0_shared_pins
57 * [11] CLKOUT_MPP_11 (out)
58 * [23] LINK_RD_IN_CP2CP (in)
59 * [25] CLKOUT_MPP_25 (out)
60 * [29] AVS_FB_IN_CP2CP (in)
61 * [32,34] GE_MDIO/MDC
62 * [33] GPIO: GE_INT#/push button/Wake
63 * [35] MSS_GPIO[3]: MSS_PWDN
64 * [36] MSS_GPIO[5]: MSS_VTT_EN
65 * [37-38] I2C0
66 * [39] PTP_CLK
67 * [40-41] SATA[0/1]_PRESENT_ACTIVEn
68 * [42-43] XG_MDC/XG_MDIO (XSMI)
69 * [44-55] RGMII1
70 * [56-62] SD
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +020071 */
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030072 /* 0 1 2 3 4 5 6 7 8 9 */
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +020073 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
74 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
75 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030076 0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5
77 0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1
78 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
79 0xe 0xe 0xe>;
80};
81
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +020082&cp0_comphy {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030083 /* Serdes Configuration:
84 * Lane 0: PCIe0 (x1)
85 * Lane 1: SATA0
Stefan Roesecb686452017-04-24 18:45:21 +030086 * Lane 2: SFI (10G)
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030087 * Lane 3: SATA1
88 * Lane 4: USB3_HOST1
89 * Lane 5: PCIe2 (x1)
90 */
91 phy0 {
Igal Liberman2dbba242017-04-26 15:40:00 +030092 phy-type = <COMPHY_TYPE_PEX0>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030093 };
94 phy1 {
Igal Liberman2dbba242017-04-26 15:40:00 +030095 phy-type = <COMPHY_TYPE_SATA0>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030096 };
97 phy2 {
Igal Liberman341e5482018-05-14 11:20:54 +030098 phy-type = <COMPHY_TYPE_SFI0>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +030099 };
100 phy3 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300101 phy-type = <COMPHY_TYPE_SATA1>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300102 };
103 phy4 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300104 phy-type = <COMPHY_TYPE_USB3_HOST1>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300105 };
106 phy5 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300107 phy-type = <COMPHY_TYPE_PEX2>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300108 };
109};
110
111/* CON6 on CP0 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200112&cp0_pcie0 {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300113 status = "okay";
114};
115
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200116&cp0_pcie1 {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300117 status = "disabled";
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200118};
Stefan Roesebf2150b2016-10-25 10:10:32 +0200119
120/* CON5 on CP0 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200121&cp0_pcie2 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200122 status = "okay";
123};
124
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200125&cp0_i2c0 {
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200126 pinctrl-names = "default";
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200127 pinctrl-0 = <&cp0_i2c0_pins>;
Stefan Roesebf2150b2016-10-25 10:10:32 +0200128 status = "okay";
129 clock-frequency = <100000>;
130};
131
132/* CON4 on CP0 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200133&cp0_sata0 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200134 status = "okay";
135};
136
137/* CON9 on CP0 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200138&cp0_usb3_0 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200139 status = "okay";
140};
141
142/* CON10 on CP0 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200143&cp0_usb3_1 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200144 status = "okay";
145};
146
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200147&cp0_utmi0 {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300148 status = "okay";
149};
150
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200151&cp0_utmi1 {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300152 status = "okay";
153};
154
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200155&cp0_sdhci0 {
Konstantin Porotchkin61dccf72018-05-25 14:20:53 +0800156 pinctrl-names = "default";
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200157 pinctrl-0 = <&cp0_sdhci_pins>;
Konstantin Porotchkin61dccf72018-05-25 14:20:53 +0800158 bus-width = <4>;
159 status = "okay";
160};
161
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200162&cp1_pinctl {
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200163 /* MPP Bus:
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300164 * [0-11] RGMII0
165 * [13-16] SPI1
166 * [27,31] GE_MDIO/MDC
167 * [28] SATA1_PRESENT_ACTIVEn
168 * [29-30] UART0
169 * [32-62] = 0xff: Keep default CP1_shared_pins
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200170 */
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300171 /* 0 1 2 3 4 5 6 7 8 9 */
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200172 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300173 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff
174 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa
175 0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200176 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
177 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300178 0xff 0xff 0xff>;
179};
180
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200181&cp1_comphy {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300182 /* Serdes Configuration:
183 * Lane 0: PCIe0 (x1)
184 * Lane 1: SATA0
Stefan Roesecb686452017-04-24 18:45:21 +0300185 * Lane 2: SFI (10G)
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300186 * Lane 3: SATA1
187 * Lane 4: PCIe1 (x1)
188 * Lane 5: PCIe2 (x1)
189 */
190 phy0 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300191 phy-type = <COMPHY_TYPE_PEX0>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300192 };
193 phy1 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300194 phy-type = <COMPHY_TYPE_SATA0>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300195 };
196 phy2 {
Igal Liberman341e5482018-05-14 11:20:54 +0300197 phy-type = <COMPHY_TYPE_SFI0>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300198 };
199 phy3 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300200 phy-type = <COMPHY_TYPE_SATA1>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300201 };
202 phy4 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300203 phy-type = <COMPHY_TYPE_PEX1>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300204 };
205 phy5 {
Igal Liberman2dbba242017-04-26 15:40:00 +0300206 phy-type = <COMPHY_TYPE_PEX2>;
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300207 };
208};
209
210/* CON6 on CP1 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200211&cp1_pcie0 {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300212 status = "okay";
213};
214
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200215&cp1_pcie1 {
Konstantin Porotchkin0f712f22017-03-28 18:36:35 +0300216 status = "okay";
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200217};
218
Stefan Roesebf2150b2016-10-25 10:10:32 +0200219/* CON5 on CP1 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200220&cp1_pcie2 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200221 status = "okay";
222};
223
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200224&cp1_spi1 {
Konstantin Porotchkinf99386c2016-12-08 12:22:30 +0200225 pinctrl-names = "default";
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200226 pinctrl-0 = <&cp1_spi1_pins>;
Stefan Roesebf2150b2016-10-25 10:10:32 +0200227 status = "okay";
Konstantin Porotchkin5b613d32016-12-08 12:22:27 +0200228
229 spi-flash@0 {
230 #address-cells = <1>;
231 #size-cells = <1>;
232 compatible = "jedec,spi-nor";
233 reg = <0>;
234 spi-max-frequency = <10000000>;
235
236 partitions {
237 compatible = "fixed-partitions";
238 #address-cells = <1>;
239 #size-cells = <1>;
240
241 partition@0 {
242 label = "U-Boot";
243 reg = <0 0x200000>;
244 };
245 partition@400000 {
246 label = "Filesystem";
247 reg = <0x200000 0xce0000>;
248 };
249 };
250 };
Stefan Roesebf2150b2016-10-25 10:10:32 +0200251};
252
253/* CON4 on CP1 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200254&cp1_sata0 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200255 status = "okay";
256};
257
258/* CON9 on CP1 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200259&cp1_usb3_0 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200260 status = "okay";
261};
262
263/* CON10 on CP1 expansion */
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200264&cp1_usb3_1 {
Stefan Roesebf2150b2016-10-25 10:10:32 +0200265 status = "okay";
266};
Stefan Roese92fdaf02016-10-25 17:43:25 +0200267
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200268&cp1_utmi0 {
Stefan Roese92fdaf02016-10-25 17:43:25 +0200269 status = "okay";
270};
Thomas Petazzonia6555eb2017-02-20 12:27:25 +0100271
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200272&cp0_mdio {
Sven Auhagen88426bd2021-08-24 10:14:25 +0200273 status = "okay";
Thomas Petazzonia6555eb2017-02-20 12:27:25 +0100274 phy1: ethernet-phy@1 {
275 reg = <1>;
276 };
277};
278
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200279&cp0_ethernet {
Thomas Petazzonia6555eb2017-02-20 12:27:25 +0100280 status = "okay";
281};
282
Konstantin Porotchkina0ba97e2021-01-17 17:19:49 +0200283&cp0_eth2 {
Thomas Petazzonia6555eb2017-02-20 12:27:25 +0100284 status = "okay";
285 phy = <&phy1>;
286 phy-mode = "rgmii-id";
287};