| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 2 | /* |
| Eric Nelson | d8acc9d | 2018-01-18 08:36:26 -0700 | [diff] [blame] | 3 | * Copyright (C) 2010-2018 Freescale Semiconductor, Inc. |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 4 | * |
| Eric Nelson | d8acc9d | 2018-01-18 08:36:26 -0700 | [diff] [blame] | 5 | * Configuration settings for the virtual mx6memcal board. |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 6 | */ |
| 7 | |||||
| 8 | #ifndef __CONFIG_H | ||||
| 9 | #define __CONFIG_H | ||||
| 10 | |||||
| 11 | /* SPL */ | ||||
| 12 | |||||
| 13 | #include "mx6_common.h" | ||||
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 14 | |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 15 | #ifdef CONFIG_SERIAL_CONSOLE_UART1 |
| 16 | #if defined(CONFIG_MX6SL) | ||||
| Tom Rini | 4db3866 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 17 | #define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 18 | #else |
| Tom Rini | 4db3866 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 19 | #define CFG_MXC_UART_BASE UART1_BASE |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 20 | #endif |
| 21 | #elif defined(CONFIG_SERIAL_CONSOLE_UART2) | ||||
| Tom Rini | 4db3866 | 2022-12-04 10:04:55 -0500 | [diff] [blame] | 22 | #define CFG_MXC_UART_BASE UART2_BASE |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 23 | #else |
| 24 | #error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) | ||||
| 25 | #endif | ||||
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 26 | |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 27 | /* Physical Memory Map */ |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 28 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
| 29 | |||||
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 30 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 31 | #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 32 | #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE | ||||
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 33 | |
| Tom Rini | dd11fdc | 2022-12-04 10:04:56 -0500 | [diff] [blame] | 34 | #define CFG_MXC_USB_PORTSC PORT_PTS_UTMI |
| Eric Nelson | 0093b3f | 2018-01-18 07:47:32 -0700 | [diff] [blame] | 35 | |
| Eric Nelson | baefb63 | 2017-12-11 13:52:11 -0200 | [diff] [blame] | 36 | #endif /* __CONFIG_H */ |