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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Peter Howarda868e442015-03-23 09:19:56 +11002/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Peter Howarda868e442015-03-23 09:19:56 +11008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
Peter Howarda868e442015-03-23 09:19:56 +110016#undef CONFIG_USE_SPIFLASH
17#undef CONFIG_SYS_USE_NOR
Peter Howarda868e442015-03-23 09:19:56 +110018
19/*
Lokesh Vutlad6d8c4d2018-03-16 18:52:21 +053020* Disable DM_* for SPL build and can be re-enabled after adding
21* DM support in SPL
22*/
23#ifdef CONFIG_SPL_BUILD
24#undef CONFIG_DM_I2C
25#undef CONFIG_DM_I2C_COMPAT
26#endif
27/*
Peter Howarda868e442015-03-23 09:19:56 +110028 * SoC Configuration
29 */
30#define CONFIG_MACH_OMAPL138_LCDK
Peter Howarda868e442015-03-23 09:19:56 +110031#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
32#define CONFIG_SYS_OSCIN_FREQ 24000000
33#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
34#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
35#define CONFIG_SYS_HZ 1000
36#define CONFIG_SKIP_LOWLEVEL_INIT
Peter Howarda868e442015-03-23 09:19:56 +110037
38/*
39 * Memory Info
40 */
41#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
42#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
43#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
44#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
45
Adam Ford15b8c752019-02-25 21:53:46 -060046#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
47#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
48
Peter Howarda868e442015-03-23 09:19:56 +110049/* memtest start addr */
50#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
51
52/* memtest will be run on 16MB */
53#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
54
Peter Howarda868e442015-03-23 09:19:56 +110055#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
56 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
57 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
58 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
59 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
60 DAVINCI_SYSCFG_SUSPSRC_I2C)
61
62/*
63 * PLL configuration
64 */
Peter Howarda868e442015-03-23 09:19:56 +110065
David Lechnerdc734832018-03-14 20:36:30 -050066/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
67#define CONFIG_SYS_DA850_PLL0_PLLM 18
Peter Howarda868e442015-03-23 09:19:56 +110068#define CONFIG_SYS_DA850_PLL1_PLLM 21
69
70/*
Fabien Parenta5ab44f2016-11-29 14:23:39 +010071 * DDR2 memory configuration
72 */
73#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
74 DV_DDR_PHY_EXT_STRBEN | \
75 (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
76
77#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
78 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
79 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
80 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
81 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
82 (4 << DV_DDR_SDCR_CL_SHIFT) | \
83 (3 << DV_DDR_SDCR_IBANK_SHIFT) | \
84 (2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
85
86/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
87#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
88
89#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
90 (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \
91 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
92 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
93 (2 << DV_DDR_SDTMR1_WR_SHIFT) | \
94 (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \
95 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
96 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
97 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
98
99#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
100 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
101 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
102 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
Sekhar Nori264e4202017-06-02 18:07:12 +0530103 (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
Fabien Parenta5ab44f2016-11-29 14:23:39 +0100104 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
105 (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
106 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
107
108#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
109#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
110
111/*
Peter Howarda868e442015-03-23 09:19:56 +1100112 * Serial Driver info
113 */
Lokesh Vutlad6d8c4d2018-03-16 18:52:21 +0530114#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
115#if !defined(CONFIG_DM_SERIAL)
Peter Howarda868e442015-03-23 09:19:56 +1100116#define CONFIG_SYS_NS16550_SERIAL
117#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
118#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
119#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Peter Howarda868e442015-03-23 09:19:56 +1100120#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Lokesh Vutlad6d8c4d2018-03-16 18:52:21 +0530121#endif
Peter Howarda868e442015-03-23 09:19:56 +1100122
Peter Howarda868e442015-03-23 09:19:56 +1100123#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
124#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Peter Howarda868e442015-03-23 09:19:56 +1100125
126#ifdef CONFIG_USE_SPIFLASH
Peter Howarda868e442015-03-23 09:19:56 +1100127#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
128#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
129#endif
130
131/*
132 * I2C Configuration
133 */
Peter Howarda868e442015-03-23 09:19:56 +1100134#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
135#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
136#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
137
138/*
139 * Flash & Environment
140 */
Adam Ford8d0d6bc2018-07-10 06:47:33 -0500141#ifdef CONFIG_NAND
Peter Howarda868e442015-03-23 09:19:56 +1100142#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
143#define CONFIG_ENV_SIZE (128 << 9)
144#define CONFIG_SYS_NAND_USE_FLASH_BBT
145#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
146#define CONFIG_SYS_NAND_PAGE_2K
Peter Howarda868e442015-03-23 09:19:56 +1100147#define CONFIG_SYS_NAND_CS 3
148#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Fabien Parent1dbab272016-11-29 14:31:31 +0100149#define CONFIG_SYS_NAND_MASK_CLE 0x10
Fabien Parentef044792016-11-29 14:31:32 +0100150#define CONFIG_SYS_NAND_MASK_ALE 0x8
Peter Howarda868e442015-03-23 09:19:56 +1100151#undef CONFIG_SYS_NAND_HW_ECC
152#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Fabien Parentc69a05d2016-11-29 14:31:34 +0100153#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Fabien Parent2b2cab22016-12-05 19:15:21 +0100154#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
Fabien Parentc69a05d2016-11-29 14:31:34 +0100155#define CONFIG_SYS_NAND_5_ADDR_CYCLE
156#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
157#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
Fabien Parentc0c10442016-12-05 19:15:20 +0100158#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Fabien Parentc69a05d2016-11-29 14:31:34 +0100159#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
160#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
161#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
162 CONFIG_SYS_NAND_U_BOOT_SIZE - \
163 CONFIG_SYS_MALLOC_LEN - \
164 GENERATED_GBL_DATA_SIZE)
165#define CONFIG_SYS_NAND_ECCPOS { \
Fabien Parent2b2cab22016-12-05 19:15:21 +0100166 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
167 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
168 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
169 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
Fabien Parentc69a05d2016-11-29 14:31:34 +0100170#define CONFIG_SYS_NAND_PAGE_COUNT 64
171#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
172#define CONFIG_SYS_NAND_ECCSIZE 512
173#define CONFIG_SYS_NAND_ECCBYTES 10
174#define CONFIG_SYS_NAND_OOBSIZE 64
175#define CONFIG_SPL_NAND_BASE
176#define CONFIG_SPL_NAND_DRIVERS
177#define CONFIG_SPL_NAND_ECC
Fabien Parentc69a05d2016-11-29 14:31:34 +0100178#define CONFIG_SPL_NAND_LOAD
Peter Howarda868e442015-03-23 09:19:56 +1100179#endif
180
181#ifdef CONFIG_SYS_USE_NOR
Peter Howarda868e442015-03-23 09:19:56 +1100182#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
183#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
184#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
185#define CONFIG_ENV_SIZE (128 << 10)
186#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
187#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
188#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
189 + 3)
190#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
191#endif
192
193#ifdef CONFIG_USE_SPIFLASH
Peter Howarda868e442015-03-23 09:19:56 +1100194#define CONFIG_ENV_SIZE (64 << 10)
195#define CONFIG_ENV_OFFSET (256 << 10)
196#define CONFIG_ENV_SECT_SIZE (64 << 10)
Peter Howarda868e442015-03-23 09:19:56 +1100197#endif
198
199/*
200 * Network & Ethernet Configuration
201 */
202#ifdef CONFIG_DRIVER_TI_EMAC
Peter Howarda868e442015-03-23 09:19:56 +1100203#undef CONFIG_DRIVER_TI_EMAC_USE_RMII
204#define CONFIG_BOOTP_DEFAULT
Peter Howarda868e442015-03-23 09:19:56 +1100205#define CONFIG_BOOTP_DNS2
206#define CONFIG_BOOTP_SEND_HOSTNAME
207#define CONFIG_NET_RETRY_COUNT 10
Peter Howarda868e442015-03-23 09:19:56 +1100208#endif
209
210/*
211 * U-Boot general configuration
212 */
Fabien Parent963ed6f2016-12-06 15:45:09 +0100213#define CONFIG_BOOTFILE "zImage" /* Boot file name */
Peter Howarda868e442015-03-23 09:19:56 +1100214#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Peter Howarda868e442015-03-23 09:19:56 +1100215#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
216#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
Peter Howarda868e442015-03-23 09:19:56 +1100217#define CONFIG_MX_CYCLIC
Peter Howarda868e442015-03-23 09:19:56 +1100218
219/*
220 * Linux Information
221 */
222#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
223#define CONFIG_CMDLINE_TAG
224#define CONFIG_REVISION_TAG
225#define CONFIG_SETUP_MEMORY_TAGS
Fabien Parentf96ab6a2016-11-29 17:15:02 +0100226#define CONFIG_BOOTCOMMAND \
Sekhar Nori1120dda2017-04-06 14:52:57 +0530227 "run envboot; " \
Sekhar Nori4c8865a2017-04-06 14:52:53 +0530228 "run mmcboot; "
Sekhar Nori6e806962017-04-06 14:52:55 +0530229
230#define DEFAULT_LINUX_BOOT_ENV \
231 "loadaddr=0xc0700000\0" \
Fabien Parent5ca28f62016-11-29 17:15:03 +0100232 "fdtaddr=0xc0600000\0" \
Sekhar Nori6e806962017-04-06 14:52:55 +0530233 "scriptaddr=0xc0600000\0"
234
Sekhar Nori1120dda2017-04-06 14:52:57 +0530235#include <environment/ti/mmc.h>
236
Sekhar Nori6e806962017-04-06 14:52:55 +0530237#define CONFIG_EXTRA_ENV_SETTINGS \
238 DEFAULT_LINUX_BOOT_ENV \
Sekhar Nori1120dda2017-04-06 14:52:57 +0530239 DEFAULT_MMC_TI_ARGS \
240 "bootpart=0:2\0" \
241 "bootdir=/boot\0" \
242 "bootfile=zImage\0" \
Fabien Parent5ca28f62016-11-29 17:15:03 +0100243 "fdtfile=da850-lcdk.dtb\0" \
Sekhar Nori1120dda2017-04-06 14:52:57 +0530244 "boot_fdt=yes\0" \
245 "boot_fit=0\0" \
246 "console=ttyS2,115200n8\0"
Peter Howarda868e442015-03-23 09:19:56 +1100247
Peter Howarda868e442015-03-23 09:19:56 +1100248#ifdef CONFIG_CMD_BDI
249#define CONFIG_CLOCKS
250#endif
251
Adam Ford8d0d6bc2018-07-10 06:47:33 -0500252#if !defined(CONFIG_NAND) && \
Peter Howarda868e442015-03-23 09:19:56 +1100253 !defined(CONFIG_SYS_USE_NOR) && \
254 !defined(CONFIG_USE_SPIFLASH)
Peter Howarda868e442015-03-23 09:19:56 +1100255#define CONFIG_ENV_SIZE (16 << 10)
Peter Howarda868e442015-03-23 09:19:56 +1100256#endif
257
258/* SD/MMC */
Peter Howarda868e442015-03-23 09:19:56 +1100259
260#ifdef CONFIG_ENV_IS_IN_MMC
261#undef CONFIG_ENV_SIZE
262#undef CONFIG_ENV_OFFSET
263#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
264#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
Peter Howarda868e442015-03-23 09:19:56 +1100265#endif
266
267#ifndef CONFIG_DIRECT_NOR_BOOT
268/* defines for SPL */
Peter Howarda868e442015-03-23 09:19:56 +1100269#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
270 CONFIG_SYS_MALLOC_LEN)
271#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Peter Howarda868e442015-03-23 09:19:56 +1100272#define CONFIG_SPL_STACK 0x8001ff00
273#define CONFIG_SPL_TEXT_BASE 0x80000000
274#define CONFIG_SPL_MAX_FOOTPRINT 32768
275#define CONFIG_SPL_PAD_TO 32768
276#endif
277
278/* additions for new relocation code, must added to all boards */
279#define CONFIG_SYS_SDRAM_BASE 0xc0000000
280#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
281 GENERATED_GBL_DATA_SIZE)
Simon Glass89f5eaa2017-05-17 08:23:09 -0600282
283#include <asm/arch/hardware.h>
284
Peter Howarda868e442015-03-23 09:19:56 +1100285#endif /* __CONFIG_H */