| Sergey Temerkhanov | 284ca9c | 2015-10-14 09:55:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * ARM Power State and Coordination Interface (PSCI) header |
| 3 | * |
| 4 | * This header holds common PSCI defines and macros shared |
| 5 | * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. |
| 6 | * |
| 7 | * Copyright (C) 2014 Linaro Ltd. |
| 8 | * Author: Anup Patel <anup.patel@linaro.org> |
| 9 | */ |
| 10 | |
| 11 | #ifndef _UAPI_LINUX_PSCI_H |
| 12 | #define _UAPI_LINUX_PSCI_H |
| 13 | |
| 14 | /* |
| 15 | * PSCI v0.1 interface |
| 16 | * |
| 17 | * The PSCI v0.1 function numbers are implementation defined. |
| 18 | * |
| 19 | * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, |
| 20 | * INVALID_PARAMS, and DENIED defined below are applicable |
| 21 | * to PSCI v0.1. |
| 22 | */ |
| 23 | |
| 24 | /* PSCI v0.2 interface */ |
| 25 | #define PSCI_0_2_FN_BASE 0x84000000 |
| 26 | #define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) |
| 27 | #define PSCI_0_2_64BIT 0x40000000 |
| 28 | #define PSCI_0_2_FN64_BASE \ |
| 29 | (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) |
| 30 | #define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) |
| 31 | |
| 32 | #define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) |
| 33 | #define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) |
| 34 | #define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) |
| 35 | #define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) |
| 36 | #define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) |
| 37 | #define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) |
| 38 | #define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) |
| 39 | #define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) |
| 40 | #define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) |
| 41 | #define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) |
| 42 | |
| 43 | #define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) |
| 44 | #define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) |
| 45 | #define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) |
| 46 | #define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) |
| 47 | #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) |
| 48 | |
| 49 | /* PSCI v0.2 power state encoding for CPU_SUSPEND function */ |
| 50 | #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff |
| 51 | #define PSCI_0_2_POWER_STATE_ID_SHIFT 0 |
| 52 | #define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 |
| 53 | #define PSCI_0_2_POWER_STATE_TYPE_MASK \ |
| 54 | (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) |
| 55 | #define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 |
| 56 | #define PSCI_0_2_POWER_STATE_AFFL_MASK \ |
| 57 | (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
| 58 | |
| 59 | /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ |
| 60 | #define PSCI_0_2_AFFINITY_LEVEL_ON 0 |
| 61 | #define PSCI_0_2_AFFINITY_LEVEL_OFF 1 |
| 62 | #define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 |
| 63 | |
| 64 | /* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ |
| 65 | #define PSCI_0_2_TOS_UP_MIGRATE 0 |
| 66 | #define PSCI_0_2_TOS_UP_NO_MIGRATE 1 |
| 67 | #define PSCI_0_2_TOS_MP 2 |
| 68 | |
| 69 | /* PSCI version decoding (independent of PSCI version) */ |
| 70 | #define PSCI_VERSION_MAJOR_SHIFT 16 |
| 71 | #define PSCI_VERSION_MINOR_MASK \ |
| 72 | ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) |
| 73 | #define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK |
| 74 | #define PSCI_VERSION_MAJOR(ver) \ |
| 75 | (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) |
| 76 | #define PSCI_VERSION_MINOR(ver) \ |
| 77 | ((ver) & PSCI_VERSION_MINOR_MASK) |
| 78 | |
| 79 | /* PSCI return values (inclusive of all PSCI versions) */ |
| 80 | #define PSCI_RET_SUCCESS 0 |
| 81 | #define PSCI_RET_NOT_SUPPORTED -1 |
| 82 | #define PSCI_RET_INVALID_PARAMS -2 |
| 83 | #define PSCI_RET_DENIED -3 |
| 84 | #define PSCI_RET_ALREADY_ON -4 |
| 85 | #define PSCI_RET_ON_PENDING -5 |
| 86 | #define PSCI_RET_INTERNAL_FAILURE -6 |
| 87 | #define PSCI_RET_NOT_PRESENT -7 |
| 88 | #define PSCI_RET_DISABLED -8 |
| 89 | |
| 90 | #endif /* _UAPI_LINUX_PSCI_H */ |