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Kim Phillips1c274c42007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillips1c274c42007-07-25 19:25:33 -050012/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_QE 1 /* Has QE */
17#define CONFIG_MPC83XX 1 /* MPC83xx family */
18#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
19
20#define CONFIG_PCI 1
21#define CONFIG_83XX_GENERIC_PCI 1
22
23/*
24 * System Clock Setup
25 */
26#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
27
28#ifndef CONFIG_SYS_CLK_FREQ
29#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
30#endif
31
32/*
33 * Hardware Reset Configuration Word
34 */
35#define CFG_HRCW_LOW (\
36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
37 HRCWL_DDR_TO_SCB_CLK_2X1 |\
38 HRCWL_VCO_1X2 |\
39 HRCWL_CSB_TO_CLKIN_2X1 |\
40 HRCWL_CORE_TO_CSB_2_5X1 |\
41 HRCWL_CE_PLL_VCO_DIV_2 |\
42 HRCWL_CE_PLL_DIV_1X1 |\
43 HRCWL_CE_TO_PLL_1X3)
44
45#define CFG_HRCW_HIGH (\
46 HRCWH_PCI_HOST |\
47 HRCWH_PCI1_ARBITER_ENABLE |\
48 HRCWH_CORE_ENABLE |\
49 HRCWH_FROM_0X00000100 |\
50 HRCWH_BOOTSEQ_DISABLE |\
51 HRCWH_SW_WATCHDOG_DISABLE |\
52 HRCWH_ROM_LOC_LOCAL_16BIT |\
53 HRCWH_BIG_ENDIAN |\
54 HRCWH_LALE_NORMAL)
55
56/*
57 * System IO Config
58 */
59#define CFG_SICRL 0x00000000
60
61#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
62
63/*
64 * IMMR new address
65 */
66#define CFG_IMMR 0xE0000000
67
68/*
Michael Barkowski5bbeea82008-03-20 13:15:34 -040069 * System performance
70 */
71#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
72#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
73#define CFG_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
74
75/*
Kim Phillips1c274c42007-07-25 19:25:33 -050076 * DDR Setup
77 */
78#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
79#define CFG_SDRAM_BASE CFG_DDR_BASE
80#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
81#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
82
83#undef CONFIG_SPD_EEPROM
84#if defined(CONFIG_SPD_EEPROM)
85/* Determine DDR configuration from I2C interface
86 */
87#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
88#else
89/* Manually set up DDR parameters
90 */
91#define CFG_DDR_SIZE 64 /* MB */
Michael Barkowskifc549c82008-03-20 13:15:28 -040092#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \
Michael Barkowski5bbeea82008-03-20 13:15:34 -040093 | CSCONFIG_ODT_WR_ACS \
Michael Barkowskifc549c82008-03-20 13:15:28 -040094 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
Michael Barkowski5bbeea82008-03-20 13:15:34 -040095 /* 0x80010101 */
Michael Barkowskifc549c82008-03-20 13:15:28 -040096#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
97 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
98 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
99 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
100 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
101 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
102 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
103 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
104 /* 0x00220802 */
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400105#define CFG_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
106 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
107 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400108 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400109 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
110 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400111 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
112 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400113 /* 0x26253222 */
114#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
115 | (31 << TIMING_CFG2_CPO_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400116 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
117 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
118 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
119 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400120 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
121 /* 0x1f9048c7 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500122#define CFG_DDR_TIMING_3 0x00000000
Michael Barkowskifc549c82008-03-20 13:15:28 -0400123#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
124 /* 0x02000000 */
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400125#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400126 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400127 /* 0x44480232 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500128#define CFG_DDR_MODE2 0x8000c000
Michael Barkowskifc549c82008-03-20 13:15:28 -0400129#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
130 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
131 /* 0x03200064 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500132#define CFG_DDR_CS0_BNDS 0x00000003
Michael Barkowskifc549c82008-03-20 13:15:28 -0400133#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
134 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
135 | SDRAM_CFG_32_BE )
136 /* 0x43080000 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500137#define CFG_DDR_SDRAM_CFG2 0x00401000
138#endif
139
140/*
141 * Memory test
142 */
143#undef CFG_DRAM_TEST /* memory test, takes time */
144#define CFG_MEMTEST_START 0x00030000 /* memtest region */
145#define CFG_MEMTEST_END 0x03f00000
146
147/*
148 * The reserved memory
149 */
150#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
151
152#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
153#define CFG_RAMBOOT
154#else
155#undef CFG_RAMBOOT
156#endif
157
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200158/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kim Phillips1c274c42007-07-25 19:25:33 -0500159#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
160#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
161
162/*
163 * Initial RAM Base Address Setup
164 */
165#define CFG_INIT_RAM_LOCK 1
166#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
167#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
168#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
169#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
170
171/*
172 * Local Bus Configuration & Clock Setup
173 */
174#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
175#define CFG_LBC_LBCR 0x00000000
176
177/*
178 * FLASH on the Local Bus
179 */
180#define CFG_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200181#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Kim Phillips1c274c42007-07-25 19:25:33 -0500182#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
183#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
Kim Phillips162c41c2008-09-23 09:38:49 -0500184#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Kim Phillips1c274c42007-07-25 19:25:33 -0500185
186#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
187#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
188
189#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
190 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
191 BR_V) /* valid */
192#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
193
194#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
195#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
196
197#undef CFG_FLASH_CHECKSUM
198
199/*
200 * SDRAM on the Local Bus
201 */
202#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
203
204#ifdef CFG_LB_SDRAM
205#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
206#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
207
208#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
209#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
210
211/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
212/*
213 * Base Register 2 and Option Register 2 configure SDRAM.
214 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
215 *
216 * For BR2, need:
217 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
218 * port size = 32-bits = BR2[19:20] = 11
219 * no parity checking = BR2[21:22] = 00
220 * SDRAM for MSEL = BR2[24:26] = 011
221 * Valid = BR[31] = 1
222 *
223 * 0 4 8 12 16 20 24 28
224 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
225 *
226 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
227 * the top 17 bits of BR2.
228 */
229
230#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
231
232/*
233 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
234 *
235 * For OR2, need:
236 * 64MB mask for AM, OR2[0:7] = 1111 1100
237 * XAM, OR2[17:18] = 11
238 * 9 columns OR2[19-21] = 010
239 * 13 rows OR2[23-25] = 100
240 * EAD set for extra time OR[31] = 1
241 *
242 * 0 4 8 12 16 20 24 28
243 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
244 */
245
246#define CFG_OR2_PRELIM 0xfc006901
247
248#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
249#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
250
251/*
252 * LSDMR masks
253 */
254#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
255#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
256#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
257#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
258#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
259#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
260#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
261#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
262
263#define CFG_LBC_LSDMR_COMMON 0x0063b723
264
265/*
266 * SDRAM Controller configuration sequence.
267 */
268#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
269 | CFG_LBC_LSDMR_OP_PCHALL)
270#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
271 | CFG_LBC_LSDMR_OP_ARFRSH)
272#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
273 | CFG_LBC_LSDMR_OP_ARFRSH)
274#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
275 | CFG_LBC_LSDMR_OP_MRW)
276#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
277 | CFG_LBC_LSDMR_OP_NORMAL)
278
279#endif
280
281/*
282 * Windows to access PIB via local bus
283 */
284#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
285#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
286
287/*
288 * Serial Port
289 */
290#define CONFIG_CONS_INDEX 1
291#undef CONFIG_SERIAL_SOFTWARE_FIFO
292#define CFG_NS16550
293#define CFG_NS16550_SERIAL
294#define CFG_NS16550_REG_SIZE 1
295#define CFG_NS16550_CLK get_bus_freq(0)
296
297#define CFG_BAUDRATE_TABLE \
298 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
299
300#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
301#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
302
303#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
304/* Use the HUSH parser */
305#define CFG_HUSH_PARSER
306#ifdef CFG_HUSH_PARSER
307#define CFG_PROMPT_HUSH_PS2 "> "
308#endif
309
310/* pass open firmware flat tree */
311#define CONFIG_OF_LIBFDT 1
312#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600313#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillips1c274c42007-07-25 19:25:33 -0500314
315/* I2C */
316#define CONFIG_HARD_I2C /* I2C with hardware support */
317#undef CONFIG_SOFT_I2C /* I2C bit-banged */
318#define CONFIG_FSL_I2C
319#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
320#define CFG_I2C_SLAVE 0x7F
321#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
322#define CFG_I2C_OFFSET 0x3000
323
324/*
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400325 * Config on-board EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500326 */
Michael Barkowski5b2793a2008-03-27 14:34:43 -0400327#define CFG_I2C_EEPROM_ADDR 0x50
328#define CFG_I2C_EEPROM_ADDR_LEN 2
329#define CFG_EEPROM_PAGE_WRITE_BITS 6
330#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
331#define CFG_EEPROM_PAGE_WRITE_ENABLE
Kim Phillips1c274c42007-07-25 19:25:33 -0500332
333/*
334 * General PCI
335 * Addresses are mapped 1-1.
336 */
337#define CFG_PCI1_MEM_BASE 0x80000000
338#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
339#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
340#define CFG_PCI1_MMIO_BASE 0x90000000
341#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
342#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
343#define CFG_PCI1_IO_BASE 0xd0000000
344#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
345#define CFG_PCI1_IO_SIZE 0x04000000 /* 64M */
346
347#ifdef CONFIG_PCI
Michael Barkowski8f325cf2008-03-28 15:15:38 -0400348#define CONFIG_PCI_SKIP_HOST_BRIDGE
Kim Phillips1c274c42007-07-25 19:25:33 -0500349#define CONFIG_NET_MULTI
350#define CONFIG_PCI_PNP /* do pci plug-and-play */
351
352#undef CONFIG_EEPRO100
353#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
354#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
355
356#endif /* CONFIG_PCI */
357
358
359#ifndef CONFIG_NET_MULTI
360#define CONFIG_NET_MULTI 1
361#endif
362
363/*
364 * QE UEC ethernet configuration
365 */
366#define CONFIG_UEC_ETH
Kim Phillips711a7942008-01-15 14:05:14 -0600367#define CONFIG_ETHPRIME "FSL UEC0"
Kim Phillips1c274c42007-07-25 19:25:33 -0500368
369#define CONFIG_UEC_ETH1 /* ETH3 */
370
371#ifdef CONFIG_UEC_ETH1
372#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
373#define CFG_UEC1_RX_CLK QE_CLK9
374#define CFG_UEC1_TX_CLK QE_CLK10
375#define CFG_UEC1_ETH_TYPE FAST_ETH
376#define CFG_UEC1_PHY_ADDR 4
377#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
378#endif
379
380#define CONFIG_UEC_ETH2 /* ETH4 */
381
382#ifdef CONFIG_UEC_ETH2
383#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
384#define CFG_UEC2_RX_CLK QE_CLK16
385#define CFG_UEC2_TX_CLK QE_CLK3
386#define CFG_UEC2_ETH_TYPE FAST_ETH
387#define CFG_UEC2_PHY_ADDR 0
388#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
389#endif
390
391/*
392 * Environment
393 */
394#ifndef CFG_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200395 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200396 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
397 #define CONFIG_ENV_SECT_SIZE 0x20000
398 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500399#else
400 #define CFG_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200401 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200402 #define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
403 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500404#endif
405
406#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
407#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
408
409/*
410 * BOOTP options
411 */
412#define CONFIG_BOOTP_BOOTFILESIZE
413#define CONFIG_BOOTP_BOOTPATH
414#define CONFIG_BOOTP_GATEWAY
415#define CONFIG_BOOTP_HOSTNAME
416
417/*
418 * Command line configuration.
419 */
420#include <config_cmd_default.h>
421
422#define CONFIG_CMD_PING
423#define CONFIG_CMD_I2C
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400424#define CONFIG_CMD_EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500425#define CONFIG_CMD_ASKENV
426
427#if defined(CONFIG_PCI)
428 #define CONFIG_CMD_PCI
429#endif
430#if defined(CFG_RAMBOOT)
431 #undef CONFIG_CMD_ENV
432 #undef CONFIG_CMD_LOADS
433#endif
434
435#undef CONFIG_WATCHDOG /* watchdog disabled */
436
437/*
438 * Miscellaneous configurable options
439 */
440#define CFG_LONGHELP /* undef to save memory */
441#define CFG_LOAD_ADDR 0x2000000 /* default load address */
442#define CFG_PROMPT "=> " /* Monitor Command Prompt */
443
444#if (CONFIG_CMD_KGDB)
445 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
446#else
447 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
448#endif
449
450#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
451#define CFG_MAXARGS 16 /* max number of command args */
452#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
453#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
454
455/*
456 * For booting Linux, the board info and command line data
457 * have to be in the first 8 MB of memory, since this is
458 * the maximum mapped by the Linux kernel during initialization.
459 */
460#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
461
462/*
463 * Core HID Setup
464 */
465#define CFG_HID0_INIT 0x000000000
466#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
467#define CFG_HID2 HID2_HBE
468
469/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500470 * MMU Setup
471 */
Becky Bruce31d82672008-05-08 19:02:12 -0500472#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Kim Phillips1c274c42007-07-25 19:25:33 -0500473
474/* DDR: cache cacheable */
475#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
476#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
477#define CFG_DBAT0L CFG_IBAT0L
478#define CFG_DBAT0U CFG_IBAT0U
479
480/* IMMRBAR & PCI IO: cache-inhibit and guarded */
481#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
482 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
483#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
484#define CFG_DBAT1L CFG_IBAT1L
485#define CFG_DBAT1U CFG_IBAT1U
486
487/* FLASH: icache cacheable, but dcache-inhibit and guarded */
488#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
489#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
490#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \
491 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
492#define CFG_DBAT2U CFG_IBAT2U
493
494#define CFG_IBAT3L (0)
495#define CFG_IBAT3U (0)
496#define CFG_DBAT3L CFG_IBAT3L
497#define CFG_DBAT3U CFG_IBAT3U
498
499/* Stack in dcache: cacheable, no memory coherence */
500#define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10)
501#define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
502#define CFG_DBAT4L CFG_IBAT4L
503#define CFG_DBAT4U CFG_IBAT4U
504
505#ifdef CONFIG_PCI
506/* PCI MEM space: cacheable */
507#define CFG_IBAT5L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
508#define CFG_IBAT5U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
509#define CFG_DBAT5L CFG_IBAT5L
510#define CFG_DBAT5U CFG_IBAT5U
511/* PCI MMIO space: cache-inhibit and guarded */
512#define CFG_IBAT6L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
513 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
514#define CFG_IBAT6U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
515#define CFG_DBAT6L CFG_IBAT6L
516#define CFG_DBAT6U CFG_IBAT6U
517#else
518#define CFG_IBAT5L (0)
519#define CFG_IBAT5U (0)
520#define CFG_IBAT6L (0)
521#define CFG_IBAT6U (0)
522#define CFG_DBAT5L CFG_IBAT5L
523#define CFG_DBAT5U CFG_IBAT5U
524#define CFG_DBAT6L CFG_IBAT6L
525#define CFG_DBAT6U CFG_IBAT6U
526#endif
527
528/* Nothing in BAT7 */
529#define CFG_IBAT7L (0)
530#define CFG_IBAT7U (0)
531#define CFG_DBAT7L CFG_IBAT7L
532#define CFG_DBAT7U CFG_IBAT7U
533
534/*
535 * Internal Definitions
536 *
537 * Boot Flags
538 */
539#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
540#define BOOTFLAG_WARM 0x02 /* Software reboot */
541
542#if (CONFIG_CMD_KGDB)
543#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
544#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
545#endif
546
547/*
548 * Environment Configuration
549 */
550#define CONFIG_ENV_OVERWRITE
551
Kim Phillips977b5752008-01-09 15:24:06 -0600552#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
Kim Phillips1c274c42007-07-25 19:25:33 -0500553#define CONFIG_ETHADDR 00:04:9f:ef:03:01
554#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
555#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
556
Michael Barkowski5b2793a2008-03-27 14:34:43 -0400557/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
558#define CFG_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
559
Kim Phillips1c274c42007-07-25 19:25:33 -0500560#define CONFIG_IPADDR 10.0.0.2
561#define CONFIG_SERVERIP 10.0.0.1
562#define CONFIG_GATEWAYIP 10.0.0.1
563#define CONFIG_NETMASK 255.0.0.0
564#define CONFIG_NETDEV eth1
565
566#define CONFIG_HOSTNAME mpc8323erdb
567#define CONFIG_ROOTPATH /nfsroot
568#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
569#define CONFIG_BOOTFILE uImage
570#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
571#define CONFIG_FDTFILE mpc832x_rdb.dtb
572
Kim Phillipsb2115752008-04-24 14:07:38 -0500573#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
Kim Phillips1c274c42007-07-25 19:25:33 -0500574#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
575#define CONFIG_BAUDRATE 115200
576
577#define XMK_STR(x) #x
578#define MK_STR(x) XMK_STR(x)
579
580#define CONFIG_EXTRA_ENV_SETTINGS \
581 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
582 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
583 "tftpflash=tftp $loadaddr $uboot;" \
584 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
585 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
586 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
587 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
588 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
589 "fdtaddr=400000\0" \
590 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
591 "ramdiskaddr=1000000\0" \
592 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
593 "console=ttyS0\0" \
594 "setbootargs=setenv bootargs " \
595 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
596 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
598 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
599
600#define CONFIG_NFSBOOTCOMMAND \
601 "setenv rootdev /dev/nfs;" \
602 "run setbootargs;" \
603 "run setipargs;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr - $fdtaddr"
607
608#define CONFIG_RAMBOOTCOMMAND \
609 "setenv rootdev /dev/ram;" \
610 "run setbootargs;" \
611 "tftp $ramdiskaddr $ramdiskfile;" \
612 "tftp $loadaddr $bootfile;" \
613 "tftp $fdtaddr $fdtfile;" \
614 "bootm $loadaddr $ramdiskaddr $fdtaddr"
615
616#undef MK_STR
617#undef XMK_STR
618
619#endif /* __CONFIG_H */