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TsiChungLiew57a12722008-01-15 14:15:46 -06001/*
2 * Configuation settings for the Freescale MCF5475 board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _M5475EVB_H
31#define _M5475EVB_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF547x_8x /* define processor family */
38#define CONFIG_M547x /* define processor type */
39#define CONFIG_M5475 /* define processor type */
40
TsiChungLiew57a12722008-01-15 14:15:46 -060041#define CONFIG_MCFUART
42#define CFG_UART_PORT (0)
43#define CONFIG_BAUDRATE 115200
44#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
45
46#define CONFIG_HW_WATCHDOG
47#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
48
49/* Command line configuration */
50#include <config_cmd_default.h>
51
52#define CONFIG_CMD_CACHE
53#undef CONFIG_CMD_DATE
54#define CONFIG_CMD_ELF
55#define CONFIG_CMD_FLASH
56#define CONFIG_CMD_I2C
57#define CONFIG_CMD_MEMORY
58#define CONFIG_CMD_MISC
59#define CONFIG_CMD_MII
60#define CONFIG_CMD_NET
61#define CONFIG_CMD_PCI
62#define CONFIG_CMD_PING
63#define CONFIG_CMD_REGINFO
64#define CONFIG_CMD_USB
65
66#define CONFIG_SLTTMR
67
68#define CONFIG_FSLDMAFEC
69#ifdef CONFIG_FSLDMAFEC
70# define CONFIG_NET_MULTI 1
71# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050072# define CONFIG_MII_INIT 1
TsiChungLiew57a12722008-01-15 14:15:46 -060073# define CONFIG_HAS_ETH1
74
TsiChung Liewf32f7fe2008-04-30 12:11:19 -050075# define CFG_DMA_USE_INTSRAM 1
TsiChungLiew57a12722008-01-15 14:15:46 -060076# define CFG_DISCOVER_PHY
77# define CFG_RX_ETH_BUFFER 32
78# define CFG_TX_ETH_BUFFER 48
79# define CFG_FAULT_ECHO_LINK_DOWN
80
81# define CFG_FEC0_PINMUX 0
82# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
83# define CFG_FEC1_PINMUX 0
84# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
85
Wolfgang Denk53677ef2008-05-20 16:00:29 +020086# define MCFFEC_TOUT_LOOP 50000
TsiChungLiew57a12722008-01-15 14:15:46 -060087/* If CFG_DISCOVER_PHY is not defined - hardcoded */
88# ifndef CFG_DISCOVER_PHY
89# define FECDUPLEX FULL
90# define FECSPEED _100BASET
91# else
92# ifndef CFG_FAULT_ECHO_LINK_DOWN
93# define CFG_FAULT_ECHO_LINK_DOWN
94# endif
95# endif /* CFG_DISCOVER_PHY */
96
97# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
98# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
99# define CONFIG_IPADDR 192.162.1.2
100# define CONFIG_NETMASK 255.255.255.0
101# define CONFIG_SERVERIP 192.162.1.1
102# define CONFIG_GATEWAYIP 192.162.1.1
103# define CONFIG_OVERWRITE_ETHADDR_ONCE
104
105#endif
106
107#ifdef CONFIG_CMD_USB
108# define CONFIG_USB_OHCI_NEW
109# define CONFIG_USB_STORAGE
110
111# ifndef CONFIG_CMD_PCI
112# define CONFIG_CMD_PCI
113# endif
114# define CONFIG_PCI_OHCI
115# define CONFIG_DOS_PARTITION
116
117# undef CFG_USB_OHCI_BOARD_INIT
118# undef CFG_USB_OHCI_CPU_INIT
119# define CFG_USB_OHCI_MAX_ROOT_PORTS 15
120# define CFG_USB_OHCI_SLOT_NAME "isp1561"
121# define CFG_OHCI_SWAP_REG_ACCESS
122#endif
123
124/* I2C */
125#define CONFIG_FSL_I2C
126#define CONFIG_HARD_I2C /* I2C with hw support */
127#undef CONFIG_SOFT_I2C /* I2C bit-banged */
128#define CFG_I2C_SPEED 80000
129#define CFG_I2C_SLAVE 0x7F
130#define CFG_I2C_OFFSET 0x00008F00
131#define CFG_IMMR CFG_MBAR
132
133/* PCI */
134#ifdef CONFIG_CMD_PCI
135#define CONFIG_PCI 1
136#define CONFIG_PCI_PNP 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500137#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600138
139#define CFG_PCI_CACHE_LINE_SIZE 8
140
141#define CFG_PCI_MEM_BUS 0x80000000
142#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
143#define CFG_PCI_MEM_SIZE 0x10000000
144
145#define CFG_PCI_IO_BUS 0x71000000
146#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
147#define CFG_PCI_IO_SIZE 0x01000000
148
149#define CFG_PCI_CFG_BUS 0x70000000
150#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
151#define CFG_PCI_CFG_SIZE 0x01000000
152#endif
153
154#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
155#define CONFIG_UDP_CHECKSUM
156
157#ifdef CONFIG_MCFFEC
158# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
159# define CONFIG_IPADDR 192.162.1.2
160# define CONFIG_NETMASK 255.255.255.0
161# define CONFIG_SERVERIP 192.162.1.1
162# define CONFIG_GATEWAYIP 192.162.1.1
163# define CONFIG_OVERWRITE_ETHADDR_ONCE
164#endif /* FEC_ENET */
165
166#define CONFIG_HOSTNAME M547xEVB
167#define CONFIG_EXTRA_ENV_SETTINGS \
168 "netdev=eth0\0" \
169 "loadaddr=10000\0" \
170 "u-boot=u-boot.bin\0" \
171 "load=tftp ${loadaddr) ${u-boot}\0" \
172 "upd=run load; run prog\0" \
173 "prog=prot off bank 1;" \
174 "era ff800000 ff82ffff;" \
175 "cp.b ${loadaddr} ff800000 ${filesize};"\
176 "save\0" \
177 ""
178
179#define CONFIG_PRAM 512 /* 512 KB */
180#define CFG_PROMPT "-> "
181#define CFG_LONGHELP /* undef to save memory */
182
183#ifdef CONFIG_CMD_KGDB
184# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
185#else
186# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
187#endif
188
189#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
190#define CFG_MAXARGS 16 /* max number of command args */
191#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
192#define CFG_LOAD_ADDR 0x00010000
193
194#define CFG_HZ 1000
195#define CFG_CLK CFG_BUSCLK
196#define CFG_CPU_CLK CFG_CLK * 2
197
198#define CFG_MBAR 0xF0000000
199#define CFG_INTSRAM (CFG_MBAR + 0x10000)
200#define CFG_INTSRAMSZ 0x8000
201
202/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
203
204/*
205 * Low Level Configuration Settings
206 * (address mappings, register initial values, etc.)
207 * You should know what you are doing if you make changes here.
208 */
209/*-----------------------------------------------------------------------
210 * Definitions for initial stack pointer and data area (in DPRAM)
211 */
212#define CFG_INIT_RAM_ADDR 0xF2000000
213#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
214#define CFG_INIT_RAM_CTRL 0x21
215#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
216#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
217#define CFG_INIT_RAM1_CTRL 0x21
218#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
219#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
220#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
221
222/*-----------------------------------------------------------------------
223 * Start addresses for the final memory configuration
224 * (Set up by the startup code)
225 * Please note that CFG_SDRAM_BASE _must_ start at 0
226 */
227#define CFG_SDRAM_BASE 0x00000000
228#define CFG_SDRAM_CFG1 0x73711630
229#define CFG_SDRAM_CFG2 0x46370000
230#define CFG_SDRAM_CTRL 0xE10B0000
231#define CFG_SDRAM_EMOD 0x40010000
232#define CFG_SDRAM_MODE 0x018D0000
233#define CFG_SDRAM_DRVSTRENGTH 0x000002AA
234#ifdef CFG_DRAMSZ1
235# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
236#else
237# define CFG_SDRAM_SIZE CFG_DRAMSZ
238#endif
239
240#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
241#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
242
243#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
244#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
245
246#define CFG_BOOTPARAMS_LEN 64*1024
247#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
248
249/*
250 * For booting Linux, the board info and command line data
251 * have to be in the first 8 MB of memory, since this is
252 * the maximum mapped by the Linux kernel during initialization ??
253 */
254#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
255
256/*-----------------------------------------------------------------------
257 * FLASH organization
258 */
259#define CFG_FLASH_CFI
260#ifdef CFG_FLASH_CFI
261# define CFG_FLASH_BASE (CFG_CS0_BASE)
262# define CFG_FLASH_CFI_DRIVER 1
263# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
264# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
265# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
266# define CFG_FLASH_USE_BUFFER_WRITE
267#ifdef CFG_NOR1SZ
268# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
269# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
270# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
271#else
272# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
273# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
274#endif
275#endif
276
277/* Configuration for environment
278 * Environment is embedded in u-boot in the second sector of the flash
279 */
280#define CFG_ENV_OFFSET 0x2000
281#define CFG_ENV_SECT_SIZE 0x2000
282#define CFG_ENV_IS_IN_FLASH 1
283#define CFG_ENV_IS_EMBEDDED 1
284
285/*-----------------------------------------------------------------------
286 * Cache Configuration
287 */
288#define CFG_CACHELINE_SIZE 16
289
290/*-----------------------------------------------------------------------
291 * Chipselect bank definitions
292 */
293/*
294 * CS0 - NOR Flash 1, 2, 4, or 8MB
295 * CS1 - NOR Flash
296 * CS2 - Available
297 * CS3 - Available
298 * CS4 - Available
299 * CS5 - Available
300 */
301#define CFG_CS0_BASE 0xFF800000
302#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
303#define CFG_CS0_CTRL 0x00101980
304
305#ifdef CFG_NOR1SZ
306#define CFG_CS1_BASE 0xF8000000
307#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
308#define CFG_CS1_CTRL 0x00000D80
309#endif
310
311#endif /* _M5475EVB_H */