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wdenka87589d2005-06-10 10:00:19 +00001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34#define CONFIG_HMI1001 1 /* HMI1001 board */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
wdenka87589d2005-06-10 10:00:19 +000041#define CONFIG_BOARD_EARLY_INIT_R
42
Becky Bruce31d82672008-05-08 19:02:12 -050043#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
wdenka87589d2005-06-10 10:00:19 +000045/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51
Wolfgang Denk08abe152005-07-21 15:23:29 +020052/* Partitions */
53#define CONFIG_DOS_PARTITION
54
wdenka87589d2005-06-10 10:00:19 +000055
Jon Loeliger48d5d102007-07-04 22:32:25 -050056/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050057 * BOOTP options
58 */
59#define CONFIG_BOOTP_BOOTFILESIZE
60#define CONFIG_BOOTP_BOOTPATH
61#define CONFIG_BOOTP_GATEWAY
62#define CONFIG_BOOTP_HOSTNAME
63
64
65/*
Jon Loeliger48d5d102007-07-04 22:32:25 -050066 * Command line configuration.
67 */
68#include <config_cmd_default.h>
69
70#define CONFIG_CMD_DATE
71#define CONFIG_CMD_DISPLAY
72#define CONFIG_CMD_DHCP
73#define CONFIG_CMD_EEPROM
74#define CONFIG_CMD_I2C
75#define CONFIG_CMD_IDE
76#define CONFIG_CMD_NFS
77#define CONFIG_CMD_PCI
78#define CONFIG_CMD_SNTP
79
wdenka87589d2005-06-10 10:00:19 +000080
81#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
82
83#if (TEXT_BASE == 0xFFF00000) /* Boot low */
84# define CFG_LOWBOOT 1
85#endif
86
87/*
88 * Autobooting
89 */
90#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
91
92#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010093 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenka87589d2005-06-10 10:00:19 +000094 "echo"
95
96#undef CONFIG_BOOTARGS
97
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100101 "nfsroot=${serverip}:${rootpath}\0" \
wdenka87589d2005-06-10 10:00:19 +0000102 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100103 "addip=setenv bootargs ${bootargs} " \
104 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
105 ":${hostname}:${netdev}:off panic=1\0" \
wdenka87589d2005-06-10 10:00:19 +0000106 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100107 "bootm ${kernel_addr}\0" \
108 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenka87589d2005-06-10 10:00:19 +0000109 "rootpath=/opt/eldk/ppc_82xx\0" \
110 ""
111
112#define CONFIG_BOOTCOMMAND "run net_nfs"
113
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200114#define CONFIG_MISC_INIT_R 1
115
wdenka87589d2005-06-10 10:00:19 +0000116/*
117 * IPB Bus clocking configuration.
118 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200119#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenka87589d2005-06-10 10:00:19 +0000120
121/*
wdenk342717f2005-06-27 13:30:03 +0000122 * I2C configuration
123 */
124#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
125#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
126
127#define CFG_I2C_SPEED 100000 /* 100 kHz */
128#define CFG_I2C_SLAVE 0x7F
129
130/*
131 * EEPROM configuration
132 */
133#define CFG_I2C_EEPROM_ADDR 0x58
134#define CFG_I2C_EEPROM_ADDR_LEN 1
135#define CFG_EEPROM_PAGE_WRITE_BITS 4
136#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
137
138/*
139 * RTC configuration
140 */
141#define CONFIG_RTC_PCF8563
142#define CFG_I2C_RTC_ADDR 0x51
143
144/*
wdenka87589d2005-06-10 10:00:19 +0000145 * Flash configuration
146 */
147#define CFG_FLASH_BASE 0xFF800000
148
149#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
150#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
151
152#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
153#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
154 (= chip selects) */
155#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
156#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
157
158#define CFG_FLASH_CFI_DRIVER
159#define CFG_FLASH_CFI
160#define CFG_FLASH_EMPTY_INFO
161#define CFG_FLASH_CFI_AMD_RESET
wdenka87589d2005-06-10 10:00:19 +0000162
163/*
164 * Environment settings
165 */
166#define CFG_ENV_IS_IN_FLASH 1
167#define CFG_ENV_SIZE 0x4000
168#define CFG_ENV_SECT_SIZE 0x20000
wdenk024447b2005-06-20 10:28:38 +0000169#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
170#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
wdenka87589d2005-06-10 10:00:19 +0000171
172/*
173 * Memory map
174 */
175#define CFG_MBAR 0xF0000000
176#define CFG_SDRAM_BASE 0x00000000
177#define CFG_DEFAULT_MBAR 0x80000000
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200178#define CFG_DISPLAY_BASE 0x80600000
179#define CFG_STATUS1_BASE 0x80600200
180#define CFG_STATUS2_BASE 0x80600300
wdenka87589d2005-06-10 10:00:19 +0000181
182/* Settings for XLB = 132 MHz */
183#define SDRAM_DDR 1
184#define SDRAM_MODE 0x018D0000
185#define SDRAM_EMODE 0x40090000
186#define SDRAM_CONTROL 0x714f0f00
187#define SDRAM_CONFIG1 0x73722930
188#define SDRAM_CONFIG2 0x47770000
189#define SDRAM_TAPDELAY 0x10000000
190
191/* Use ON-Chip SRAM until RAM will be available */
192#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
193#ifdef CONFIG_POST
194/* preserve space for the post_word at end of on-chip SRAM */
195#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
196#else
197#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
198#endif
199
200
201#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
202#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
203#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
204
205#define CFG_MONITOR_BASE TEXT_BASE
206#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
207# define CFG_RAMBOOT 1
208#endif
209
210#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk342717f2005-06-27 13:30:03 +0000211#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
wdenka87589d2005-06-10 10:00:19 +0000212#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
213
214/*
215 * Ethernet configuration
216 */
217#define CONFIG_MPC5xxx_FEC 1
218#define CONFIG_PHY_ADDR 0x00
Wolfgang Denk8d7e2732007-03-07 16:19:46 +0100219#define CONFIG_MII 1 /* MII PHY management */
wdenka87589d2005-06-10 10:00:19 +0000220
221/*
222 * GPIO configuration
223 */
224#define CFG_GPS_PORT_CONFIG 0x01051004
225
226/*
wdenka87589d2005-06-10 10:00:19 +0000227 * Miscellaneous configurable options
228 */
229#define CFG_LONGHELP /* undef to save memory */
230#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500231#if defined(CONFIG_CMD_KGDB)
wdenka87589d2005-06-10 10:00:19 +0000232#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
233#else
234#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
235#endif
236#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
237#define CFG_MAXARGS 16 /* max number of command args */
238#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
239
Jon Loeliger48d5d102007-07-04 22:32:25 -0500240#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
241#if defined(CONFIG_CMD_KGDB)
242# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
243#endif
244
wdenka87589d2005-06-10 10:00:19 +0000245/* Enable an alternate, more extensive memory test */
246#define CFG_ALT_MEMTEST
247
248#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
249#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
250
251#define CFG_LOAD_ADDR 0x100000 /* default load address */
252
253#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
254
255/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500256 * Enable loopw command.
wdenka87589d2005-06-10 10:00:19 +0000257 */
258#define CONFIG_LOOPW
259
260/*
261 * Various low-level settings
262 */
263#if defined(CONFIG_MPC5200)
264#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
265#define CFG_HID0_FINAL HID0_ICE
266#else
267#define CFG_HID0_INIT 0
268#define CFG_HID0_FINAL 0
269#endif
270
271#define CFG_BOOTCS_START CFG_FLASH_BASE
272#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
273#define CFG_BOOTCS_CFG 0x0004FB00
274#define CFG_CS0_START CFG_FLASH_BASE
275#define CFG_CS0_SIZE CFG_FLASH_SIZE
276
277/* 8Mbit SRAM @0x80100000 */
278#define CFG_CS1_START 0x80100000
279#define CFG_CS1_SIZE 0x00100000
280#define CFG_CS1_CFG 0x19B00
281
282/* FRAM 32Kbyte @0x80700000 */
283#define CFG_CS2_START 0x80700000
284#define CFG_CS2_SIZE 0x00008000
285#define CFG_CS2_CFG 0x19800
286
287/* Display H1, Status Inputs, EPLD @0x80600000 */
288#define CFG_CS3_START 0x80600000
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200289#define CFG_CS3_SIZE 0x00100000
Wolfgang Denkf7fbf262005-08-30 13:43:18 +0200290#define CFG_CS3_CFG 0x00019800
wdenka87589d2005-06-10 10:00:19 +0000291
292#define CFG_CS_BURST 0x00000000
293#define CFG_CS_DEADCYCLE 0x33333333
294
Wolfgang Denk08abe152005-07-21 15:23:29 +0200295/*-----------------------------------------------------------------------
296 * IDE/ATA stuff Supports IDE harddisk
297 *-----------------------------------------------------------------------
298 */
299
300#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
301
302#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
303#undef CONFIG_IDE_LED /* LED for ide not supported */
304
305#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
306#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
307
Wolfgang Denk9d3338d2005-08-10 10:06:25 +0200308#define CONFIG_IDE_PREINIT 1
309
Wolfgang Denk08abe152005-07-21 15:23:29 +0200310#define CFG_ATA_IDE0_OFFSET 0x0000
311
312#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
313
314/* Offset for data I/O */
315#define CFG_ATA_DATA_OFFSET (0x0060)
316
317/* Offset for normal register accesses */
318#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
319
320/* Offset for alternate registers */
321#define CFG_ATA_ALT_OFFSET (0x005C)
322
323/* Interval between registers */
324#define CFG_ATA_STRIDE 4
325
326#define CONFIG_ATAPI 1
327
Wolfgang Denkccd9d3d2005-09-03 01:21:50 +0200328#define CONFIG_VIDEO_SMI_LYNXEM
329#define CONFIG_CFB_CONSOLE
330#define CONFIG_VGA_AS_SINGLE_DEVICE
331#define CONFIG_VIDEO_LOGO
332
Wolfgang Denk98128f32005-08-16 15:17:53 +0200333/*
334 * PCI Mapping:
335 * 0x40000000 - 0x4fffffff - PCI Memory
336 * 0x50000000 - 0x50ffffff - PCI IO Space
337 */
338#define CONFIG_PCI 1
339#define CONFIG_PCI_PNP 1
340#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500341#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Wolfgang Denk98128f32005-08-16 15:17:53 +0200342
343#define CONFIG_PCI_MEM_BUS 0x40000000
344#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
345#define CONFIG_PCI_MEM_SIZE 0x10000000
346
347#define CONFIG_PCI_IO_BUS 0x50000000
348#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
349#define CONFIG_PCI_IO_SIZE 0x01000000
350
Wolfgang Denkccd9d3d2005-09-03 01:21:50 +0200351#define CFG_ISA_IO CONFIG_PCI_IO_BUS
352
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200353/*---------------------------------------------------------------------*/
354/* Display addresses */
355/*---------------------------------------------------------------------*/
356
357#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
358#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
359
wdenka87589d2005-06-10 10:00:19 +0000360#endif /* __CONFIG_H */