blob: c557ba177872483c039c275068d021dda25a691b [file] [log] [blame]
wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf4675562002-10-02 14:20:15 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf4675562002-10-02 14:20:15 +000026#ifdef CONFIG_LCD /* with LCD controller ? */
Jeroen Hofstee59155f42013-01-22 10:44:09 +000027#define CONFIG_MPC8XX_LCD
Wolfgang Denk21f971e2008-07-07 01:22:29 +020028#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
29#define CONFIG_LCD_INFO 1 /* ... and some board info */
wdenk27b207f2003-07-24 23:38:38 +000030#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenkf4675562002-10-02 14:20:15 +000031#endif
32
33#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020034#define CONFIG_SYS_SMC_RXBUFLEN 128
35#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000036#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000037
wdenkae3af052003-08-07 22:18:11 +000038#define CONFIG_BOOTCOUNT_LIMIT
39
wdenkf4675562002-10-02 14:20:15 +000040
41#define CONFIG_BOARD_TYPES 1 /* support board types */
42
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010043#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000044
45#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000046
47#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000048 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000049 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000051 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "addip=setenv bootargs ${bootargs} " \
53 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
54 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000055 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000057 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
59 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000060 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020061 "hostname=TQM823L\0" \
62 "bootfile=TQM823L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020063 "fdt_addr=40040000\0" \
64 "kernel_addr=40060000\0" \
65 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020066 "u-boot=TQM823L/u-image.bin\0" \
67 "load=tftp 200000 ${u-boot}\0" \
68 "update=prot off 40000000 +${filesize};" \
69 "era 40000000 +${filesize};" \
70 "cp.b 200000 40000000 ${filesize};" \
71 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000072 ""
73#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000074
75#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000077
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
wdenka522fa02004-01-04 22:51:12 +000080#if defined(CONFIG_LCD)
wdenkf4675562002-10-02 14:20:15 +000081# undef CONFIG_STATUS_LED /* disturbs display */
82#else
83# define CONFIG_STATUS_LED 1 /* Status LED enabled */
84#endif /* CONFIG_LCD */
85
wdenka522fa02004-01-04 22:51:12 +000086#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkf4675562002-10-02 14:20:15 +000087
Jon Loeliger37d4bb72007-07-09 21:38:02 -050088/*
89 * BOOTP options
90 */
91#define CONFIG_BOOTP_SUBNETMASK
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_BOOTFILESIZE
96
wdenkf4675562002-10-02 14:20:15 +000097#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
100#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
101
Jon Loeliger26946902007-07-04 22:30:50 -0500102/*
103 * Command line configuration.
104 */
Jon Loeliger26946902007-07-04 22:30:50 -0500105#define CONFIG_CMD_DATE
Jon Loeliger26946902007-07-04 22:30:50 -0500106#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200107#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500108
wdenk27b207f2003-07-24 23:38:38 +0000109#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger26946902007-07-04 22:30:50 -0500110 #define CONFIG_CMD_BMP
wdenk27b207f2003-07-24 23:38:38 +0000111#endif
wdenkf4675562002-10-02 14:20:15 +0000112
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200113#define CONFIG_NETCONSOLE
114
wdenkf4675562002-10-02 14:20:15 +0000115/*
116 * Miscellaneous configurable options
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000119
Wolfgang Denk2751a952006-10-28 02:29:14 +0200120#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenk6aff3112002-12-17 01:51:00 +0000121
Jon Loeliger26946902007-07-04 22:30:50 -0500122#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000124#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000126#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
132#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000135
wdenkf4675562002-10-02 14:20:15 +0000136/*
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
140 */
141/*-----------------------------------------------------------------------
142 * Internal Memory Mapped Register
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000145
146/*-----------------------------------------------------------------------
147 * Definitions for initial stack pointer and data area (in DPRAM)
148 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200150#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200151#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000153
154/*-----------------------------------------------------------------------
155 * Start addresses for the final memory configuration
156 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_SDRAM_BASE 0x00000000
160#define CONFIG_SYS_FLASH_BASE 0x40000000
161#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
162#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
163#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000164
165/*
166 * For booting Linux, the board info and command line data
167 * have to be in the first 8 MB of memory, since this is
168 * the maximum mapped by the Linux kernel during initialization.
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000171
172/*-----------------------------------------------------------------------
173 * FLASH organization
174 */
wdenkf4675562002-10-02 14:20:15 +0000175
Martin Krausee318d9e2007-09-27 11:10:08 +0200176/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200178#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
180#define CONFIG_SYS_FLASH_EMPTY_INFO
181#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
182#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
183#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000184
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200185#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200186#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
187#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000188
189/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200190#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
191#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200194
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200195#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
196
wdenkf4675562002-10-02 14:20:15 +0000197/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200198 * Dynamic MTD partition support
199 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100200#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200201#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
202#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200203#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
204
205#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
206 "128k(dtb)," \
207 "1664k(kernel)," \
208 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200209 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200210
211/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000212 * Hardware Information Block
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
215#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
216#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000217
218/*-----------------------------------------------------------------------
219 * Cache Configuration
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500222#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000224#endif
225
226/*-----------------------------------------------------------------------
227 * SYPCR - System Protection Control 11-9
228 * SYPCR can only be written once after reset!
229 *-----------------------------------------------------------------------
230 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
231 */
232#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000234 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
235#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000237#endif
238
239/*-----------------------------------------------------------------------
240 * SIUMCR - SIU Module Configuration 11-6
241 *-----------------------------------------------------------------------
242 * PCMCIA config., multi-function pin tri-state
243 */
244#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000246#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000248#endif /* CONFIG_CAN_DRIVER */
249
250/*-----------------------------------------------------------------------
251 * TBSCR - Time Base Status and Control 11-26
252 *-----------------------------------------------------------------------
253 * Clear Reference Interrupt Status, Timebase freezing enabled
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000256
257/*-----------------------------------------------------------------------
258 * RTCSC - Real-Time Clock Status and Control Register 11-27
259 *-----------------------------------------------------------------------
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000262
263/*-----------------------------------------------------------------------
264 * PISCR - Periodic Interrupt Status and Control 11-31
265 *-----------------------------------------------------------------------
266 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000269
270/*-----------------------------------------------------------------------
271 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
272 *-----------------------------------------------------------------------
273 * Reset PLL lock status sticky bit, timer expired status bit and timer
274 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000275 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000277
278/*-----------------------------------------------------------------------
279 * SCCR - System Clock and reset Control Register 15-27
280 *-----------------------------------------------------------------------
281 * Set clock output, timebase and RTC source and divider,
282 * power management and some other internal clocks
283 */
284#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000286 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
287 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000288
289/*-----------------------------------------------------------------------
290 * PCMCIA stuff
291 *-----------------------------------------------------------------------
292 *
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
295#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
296#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
297#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
298#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
299#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
300#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
301#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000302
303/*-----------------------------------------------------------------------
304 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
305 *-----------------------------------------------------------------------
306 */
307
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000308#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000309#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
310
311#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
312#undef CONFIG_IDE_LED /* LED for ide not supported */
313#undef CONFIG_IDE_RESET /* reset for ide not supported */
314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
316#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000321
322/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000324
325/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000327
328/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000330
331/*-----------------------------------------------------------------------
332 *
333 *-----------------------------------------------------------------------
334 *
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000337
338/*
339 * Init Memory Controller:
340 *
341 * BR0/1 and OR0/1 (FLASH)
342 */
343
344#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
345#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
346
347/* used to re-map FLASH both when starting from SRAM or FLASH:
348 * restrict access enough to keep SRAM working (if any)
349 * but not too much to meddle with FLASH accesses
350 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
352#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000353
354/*
355 * FLASH timing:
356 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000358 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
361#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
362#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
365#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
366#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000367
368/*
369 * BR2/3 and OR2/3 (SDRAM)
370 *
371 */
372#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
373#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
374#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
375
376/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
380#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000381
382#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
384#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000385#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
387#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
388#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
389#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000390 BR_PS_8 | BR_MS_UPMB | BR_V )
391#endif /* CONFIG_CAN_DRIVER */
392
393/*
394 * Memory Periodic Timer Prescaler
395 *
396 * The Divider for PTA (refresh timer) configuration is based on an
397 * example SDRAM configuration (64 MBit, one bank). The adjustment to
398 * the number of chip selects (NCS) and the actually needed refresh
399 * rate is done by setting MPTPR.
400 *
401 * PTA is calculated from
402 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
403 *
404 * gclk CPU clock (not bus clock!)
405 * Trefresh Refresh cycle * 4 (four word bursts used)
406 *
407 * 4096 Rows from SDRAM example configuration
408 * 1000 factor s -> ms
409 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
410 * 4 Number of refresh cycles per period
411 * 64 Refresh cycle in ms per number of rows
412 * --------------------------------------------
413 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
414 *
415 * 50 MHz => 50.000.000 / Divider = 98
416 * 66 Mhz => 66.000.000 / Divider = 129
417 * 80 Mhz => 80.000.000 / Divider = 156
418 */
wdenke9132ea2004-04-24 23:23:30 +0000419
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
421#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000422
423/*
424 * For 16 MBit, refresh rates could be 31.3 us
425 * (= 64 ms / 2K = 125 / quad bursts).
426 * For a simpler initialization, 15.6 us is used instead.
427 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
429 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000430 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
432#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000433
434/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
436#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000437
438/*
439 * MAMR settings for SDRAM
440 */
441
442/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000444 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
445 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
446/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000448 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
449 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450
Heiko Schocher7026ead2010-02-09 15:50:27 +0100451#define CONFIG_HWCONFIG 1
452
wdenkf4675562002-10-02 14:20:15 +0000453#endif /* __CONFIG_H */