blob: 30bfbf44f5c3354632e3d8680cd8cc0427ce5fea [file] [log] [blame]
Xie Xiaobo49f5bef2013-06-24 15:01:30 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
York Sun3aab0cd2013-08-12 14:57:12 -07004 * SPDX-License-Identifier: GPL-2.0+
Xie Xiaobo49f5bef2013-06-24 15:01:30 +08005 */
6
7/*
8 * QorIQ P1 Tower boards configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Ying Zhange838b0c2014-11-04 15:10:46 +080013#define CONFIG_DISPLAY_BOARDINFO
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080014#if defined(CONFIG_TWR_P1025)
15#define CONFIG_BOARDNAME "TWR-P1025"
16#define CONFIG_P1025
17#define CONFIG_PHY_ATHEROS
18#define CONFIG_QE
19#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
20#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
21#endif
22
23#ifdef CONFIG_SDCARD
24#define CONFIG_RAMBOOT_SDCARD
25#define CONFIG_SYS_RAMBOOT
26#define CONFIG_SYS_EXTRA_ENV_RELOC
27#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053028#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080029#endif
30
31#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053032#define CONFIG_SYS_TEXT_BASE 0xeff40000
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080033#endif
34
35#ifndef CONFIG_RESET_VECTOR_ADDRESS
36#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
37#endif
38
39#ifndef CONFIG_SYS_MONITOR_BASE
40#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
41#endif
42
43/* High Level Configuration Options */
44#define CONFIG_BOOKE
45#define CONFIG_E500
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080046
47#define CONFIG_MP
48
49#define CONFIG_FSL_ELBC
50#define CONFIG_PCI
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040051#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
52#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080053#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
54#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
55#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
56#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
57
58#define CONFIG_FSL_LAW
59#define CONFIG_TSEC_ENET /* tsec ethernet support */
60#define CONFIG_ENV_OVERWRITE
61
62#define CONFIG_CMD_SATA
63#define CONFIG_SATA_SIL3114
64#define CONFIG_SYS_SATA_MAX_DEVICE 2
65#define CONFIG_LIBATA
66#define CONFIG_LBA48
67
68#ifndef __ASSEMBLY__
69extern unsigned long get_board_sys_clk(unsigned long dummy);
70#endif
71#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */
72
73#define CONFIG_DDR_CLK_FREQ 66666666
74
75#define CONFIG_HWCONFIG
76/*
77 * These can be toggled for performance analysis, otherwise use default.
78 */
79#define CONFIG_L2_CACHE
80#define CONFIG_BTB
81
82#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
83
84#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
85#define CONFIG_SYS_MEMTEST_END 0x1fffffff
86#define CONFIG_PANIC_HANG /* do not reset board on panic */
87
88#define CONFIG_SYS_CCSRBAR 0xffe00000
89#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
90
91/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070092#define CONFIG_SYS_FSL_DDR3
Xie Xiaobo49f5bef2013-06-24 15:01:30 +080093
94#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
95#define CONFIG_CHIP_SELECTS_PER_CTRL 1
96
97#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
98#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
99#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
100
101#define CONFIG_NUM_DDR_CONTROLLERS 1
102#define CONFIG_DIMM_SLOTS_PER_CTLR 1
103
104/* Default settings for DDR3 */
105#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
106#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
107#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
108#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
109#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
110#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
111
112#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
113#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
114#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
115#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
116
117#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
118#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608
119#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
120#define CONFIG_SYS_DDR_RCW_1 0x00000000
121#define CONFIG_SYS_DDR_RCW_2 0x00000000
122#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */
123#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
124#define CONFIG_SYS_DDR_TIMING_4 0x00220001
125#define CONFIG_SYS_DDR_TIMING_5 0x03402400
126
127#define CONFIG_SYS_DDR_TIMING_3 0x00020000
128#define CONFIG_SYS_DDR_TIMING_0 0x00220004
129#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544
130#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de
131#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
132#define CONFIG_SYS_DDR_MODE_1 0x80461320
133#define CONFIG_SYS_DDR_MODE_2 0x00008000
134#define CONFIG_SYS_DDR_INTERVAL 0x09480000
135
136/*
137 * Memory map
138 *
139 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable
140 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
141 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
142 *
143 * Localbus
144 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable
145 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
146 *
147 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable
148 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable
149 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
150 */
151
152/*
153 * Local Bus Definitions
154 */
155#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
156#define CONFIG_SYS_FLASH_BASE 0xec000000
157
158#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
159
160#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
161 | BR_PS_16 | BR_V)
162
163#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1
164
165#define CONFIG_SYS_SSD_BASE 0xe0000000
166#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE
167#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
168 BR_PS_16 | BR_V)
169#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
170 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
171 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
172
173#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
174#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
175
176#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
177#define CONFIG_SYS_FLASH_QUIET_TEST
178#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
179
180#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
181
182#undef CONFIG_SYS_FLASH_CHECKSUM
183#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
184#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
185
186#define CONFIG_FLASH_CFI_DRIVER
187#define CONFIG_SYS_FLASH_CFI
188#define CONFIG_SYS_FLASH_EMPTY_INFO
189#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
190
191#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
192
193#define CONFIG_SYS_INIT_RAM_LOCK
194#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
195/* Initial L1 address */
196#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
197#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
198#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
199/* Size of used area in RAM */
200#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
201
202#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
203 GENERATED_GBL_DATA_SIZE)
204#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
205
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530206#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800207#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
208
209#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
210#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
211
212/* Serial Port
213 * open - index 2
214 * shorted - index 1
215 */
216#define CONFIG_CONS_INDEX 1
217#undef CONFIG_SERIAL_SOFTWARE_FIFO
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800218#define CONFIG_SYS_NS16550_SERIAL
219#define CONFIG_SYS_NS16550_REG_SIZE 1
220#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
221
222#define CONFIG_SYS_BAUDRATE_TABLE \
223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
224
225#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
226#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
227
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800228/* I2C */
229#define CONFIG_SYS_I2C
230#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
231#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */
232#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
233#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
234#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
235
236/*
237 * I2C2 EEPROM
238 */
239#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */
240#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
241#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
242
243#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23
244
245/* enable read and write access to EEPROM */
246#define CONFIG_CMD_EEPROM
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800247#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
248#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
249#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
250
251/*
252 * eSPI - Enhanced SPI
253 */
254#define CONFIG_HARD_SPI
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800255
256#if defined(CONFIG_PCI)
257/*
258 * General PCI
259 * Memory space is mapped 1-1, but I/O space must start from 0.
260 */
261
262/* controller 2, direct to uli, tgtid 2, Base address 9000 */
263#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT"
264#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
265#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
266#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
267#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
268#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
269#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
270#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
271#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
272
273/* controller 1, tgtid 1, Base address a000 */
274#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
275#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
276#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
277#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
278#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
279#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
280#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
281#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
282#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
283
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800284#define CONFIG_PCI_PNP /* do pci plug-and-play */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800285#define CONFIG_CMD_PCI
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800286
287#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
288#define CONFIG_DOS_PARTITION
289#endif /* CONFIG_PCI */
290
291#if defined(CONFIG_TSEC_ENET)
292
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800293#define CONFIG_MII /* MII PHY management */
294#define CONFIG_TSEC1
295#define CONFIG_TSEC1_NAME "eTSEC1"
296#undef CONFIG_TSEC2
297#undef CONFIG_TSEC2_NAME
298#define CONFIG_TSEC3
299#define CONFIG_TSEC3_NAME "eTSEC3"
300
301#define TSEC1_PHY_ADDR 2
302#define TSEC2_PHY_ADDR 0
303#define TSEC3_PHY_ADDR 1
304
305#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
306#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
307#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
308
309#define TSEC1_PHYIDX 0
310#define TSEC2_PHYIDX 0
311#define TSEC3_PHYIDX 0
312
313#define CONFIG_ETHPRIME "eTSEC1"
314
315#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
316
317#define CONFIG_HAS_ETH0
318#define CONFIG_HAS_ETH1
319#undef CONFIG_HAS_ETH2
320#endif /* CONFIG_TSEC_ENET */
321
322#ifdef CONFIG_QE
323/* QE microcode/firmware address */
324#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800325#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800326#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
327#endif /* CONFIG_QE */
328
329#ifdef CONFIG_TWR_P1025
330/*
331 * QE UEC ethernet configuration
332 */
333#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
334
335#undef CONFIG_UEC_ETH
336#define CONFIG_PHY_MODE_NEED_CHANGE
337
338#define CONFIG_UEC_ETH1 /* ETH1 */
339#define CONFIG_HAS_ETH0
340
341#ifdef CONFIG_UEC_ETH1
342#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
343#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
344#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
345#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
346#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */
347#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
348#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
349#endif /* CONFIG_UEC_ETH1 */
350
351#define CONFIG_UEC_ETH5 /* ETH5 */
352#define CONFIG_HAS_ETH1
353
354#ifdef CONFIG_UEC_ETH5
355#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
356#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
357#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
358#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
359#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */
360#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
361#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
362#endif /* CONFIG_UEC_ETH5 */
363#endif /* CONFIG_TWR-P1025 */
364
365/*
Yangbo Lu94b383e2014-10-16 10:58:55 +0800366 * Dynamic MTD Partition support with mtdparts
367 */
368#define CONFIG_MTD_DEVICE
369#define CONFIG_MTD_PARTITIONS
370#define CONFIG_CMD_MTDPARTS
371#define CONFIG_FLASH_CFI_MTD
372#define MTDIDS_DEFAULT "nor0=ec000000.nor"
373#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
374 "256k(dtb),5632k(kernel),57856k(fs)," \
375 "256k(qe-ucode-firmware),1280k(u-boot)"
376
377/*
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800378 * Environment
379 */
380#ifdef CONFIG_SYS_RAMBOOT
381#ifdef CONFIG_RAMBOOT_SDCARD
382#define CONFIG_ENV_IS_IN_MMC
383#define CONFIG_ENV_SIZE 0x2000
384#define CONFIG_SYS_MMC_ENV_DEV 0
385#else
386#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
387#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
388#define CONFIG_ENV_SIZE 0x2000
389#endif
390#else
391#define CONFIG_ENV_IS_IN_FLASH
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800392#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800393#define CONFIG_ENV_SIZE 0x2000
394#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
395#endif
396
397#define CONFIG_LOADS_ECHO /* echo on for serial download */
398#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
399
400/*
401 * Command line configuration.
402 */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800403#define CONFIG_CMD_IRQ
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800404#define CONFIG_CMD_REGINFO
405
406/*
407 * USB
408 */
409#define CONFIG_HAS_FSL_DR_USB
410
411#if defined(CONFIG_HAS_FSL_DR_USB)
412#define CONFIG_USB_EHCI
413
414#ifdef CONFIG_USB_EHCI
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800415#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
416#define CONFIG_USB_EHCI_FSL
417#define CONFIG_USB_STORAGE
418#endif
419#endif
420
421#define CONFIG_MMC
422
423#ifdef CONFIG_MMC
424#define CONFIG_FSL_ESDHC
425#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800426#define CONFIG_GENERIC_MMC
427#endif
428
429#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
430 || defined(CONFIG_FSL_SATA)
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800431#define CONFIG_DOS_PARTITION
432#endif
433
434#undef CONFIG_WATCHDOG /* watchdog disabled */
435
436/*
437 * Miscellaneous configurable options
438 */
439#define CONFIG_SYS_LONGHELP /* undef to save memory */
440#define CONFIG_CMDLINE_EDITING /* Command-line editing */
441#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800442#if defined(CONFIG_CMD_KGDB)
443#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
444#else
445#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
446#endif
447#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
448 /* Print Buffer Size */
449#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
450#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800451
452/*
453 * For booting Linux, the board info and command line data
454 * have to be in the first 64 MB of memory, since this is
455 * the maximum mapped by the Linux kernel during initialization.
456 */
457#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
458#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
459
460/*
461 * Environment Configuration
462 */
463#define CONFIG_HOSTNAME unknown
464#define CONFIG_ROOTPATH "/opt/nfsroot"
465#define CONFIG_BOOTFILE "uImage"
466#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
467
468/* default location for tftp and bootm */
469#define CONFIG_LOADADDR 1000000
470
Xie Xiaobo49f5bef2013-06-24 15:01:30 +0800471#define CONFIG_BOOTARGS /* the boot command will set bootargs */
472
473#define CONFIG_BAUDRATE 115200
474
475#define CONFIG_EXTRA_ENV_SETTINGS \
476"netdev=eth0\0" \
477"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
478"loadaddr=1000000\0" \
479"bootfile=uImage\0" \
480"dtbfile=twr-p1025twr.dtb\0" \
481"ramdiskfile=rootfs.ext2.gz.uboot\0" \
482"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \
483"tftpflash=tftpboot $loadaddr $uboot; " \
484 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
485 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
486 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
487 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
488 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
489"kernelflash=tftpboot $loadaddr $bootfile; " \
490 "protect off 0xefa80000 +$filesize; " \
491 "erase 0xefa80000 +$filesize; " \
492 "cp.b $loadaddr 0xefa80000 $filesize; " \
493 "protect on 0xefa80000 +$filesize; " \
494 "cmp.b $loadaddr 0xefa80000 $filesize\0" \
495"dtbflash=tftpboot $loadaddr $dtbfile; " \
496 "protect off 0xefe80000 +$filesize; " \
497 "erase 0xefe80000 +$filesize; " \
498 "cp.b $loadaddr 0xefe80000 $filesize; " \
499 "protect on 0xefe80000 +$filesize; " \
500 "cmp.b $loadaddr 0xefe80000 $filesize\0" \
501"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \
502 "protect off 0xeeb80000 +$filesize; " \
503 "erase 0xeeb80000 +$filesize; " \
504 "cp.b $loadaddr 0xeeb80000 $filesize; " \
505 "protect on 0xeeb80000 +$filesize; " \
506 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \
507"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \
508 "protect off 0xefec0000 +$filesize; " \
509 "erase 0xefec0000 +$filesize; " \
510 "cp.b $loadaddr 0xefec0000 $filesize; " \
511 "protect on 0xefec0000 +$filesize; " \
512 "cmp.b $loadaddr 0xefec0000 $filesize\0" \
513"consoledev=ttyS0\0" \
514"ramdiskaddr=2000000\0" \
515"ramdiskfile=rootfs.ext2.gz.uboot\0" \
516"fdtaddr=c00000\0" \
517"bdev=sda1\0" \
518"norbootaddr=ef080000\0" \
519"norfdtaddr=ef040000\0" \
520"ramdisk_size=120000\0" \
521"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
522"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
523
524#define CONFIG_NFSBOOTCOMMAND \
525"setenv bootargs root=/dev/nfs rw " \
526"nfsroot=$serverip:$rootpath " \
527"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
528"console=$consoledev,$baudrate $othbootargs;" \
529"tftp $loadaddr $bootfile&&" \
530"tftp $fdtaddr $fdtfile&&" \
531"bootm $loadaddr - $fdtaddr"
532
533#define CONFIG_HDBOOT \
534"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
535"console=$consoledev,$baudrate $othbootargs;" \
536"usb start;" \
537"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
538"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
539"bootm $loadaddr - $fdtaddr"
540
541#define CONFIG_USB_FAT_BOOT \
542"setenv bootargs root=/dev/ram rw " \
543"console=$consoledev,$baudrate $othbootargs " \
544"ramdisk_size=$ramdisk_size;" \
545"usb start;" \
546"fatload usb 0:2 $loadaddr $bootfile;" \
547"fatload usb 0:2 $fdtaddr $fdtfile;" \
548"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
549"bootm $loadaddr $ramdiskaddr $fdtaddr"
550
551#define CONFIG_USB_EXT2_BOOT \
552"setenv bootargs root=/dev/ram rw " \
553"console=$consoledev,$baudrate $othbootargs " \
554"ramdisk_size=$ramdisk_size;" \
555"usb start;" \
556"ext2load usb 0:4 $loadaddr $bootfile;" \
557"ext2load usb 0:4 $fdtaddr $fdtfile;" \
558"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
559"bootm $loadaddr $ramdiskaddr $fdtaddr"
560
561#define CONFIG_NORBOOT \
562"setenv bootargs root=/dev/mtdblock3 rw " \
563"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
564"bootm $norbootaddr - $norfdtaddr"
565
566#define CONFIG_RAMBOOTCOMMAND_TFTP \
567"setenv bootargs root=/dev/ram rw " \
568"console=$consoledev,$baudrate $othbootargs " \
569"ramdisk_size=$ramdisk_size;" \
570"tftp $ramdiskaddr $ramdiskfile;" \
571"tftp $loadaddr $bootfile;" \
572"tftp $fdtaddr $fdtfile;" \
573"bootm $loadaddr $ramdiskaddr $fdtaddr"
574
575#define CONFIG_RAMBOOTCOMMAND \
576"setenv bootargs root=/dev/ram rw " \
577"console=$consoledev,$baudrate $othbootargs " \
578"ramdisk_size=$ramdisk_size;" \
579"bootm 0xefa80000 0xeeb80000 0xefe80000"
580
581#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
582
583#endif /* __CONFIG_H */