blob: 5d694d85ef687586b7559fa635ae87ac69091d46 [file] [log] [blame]
Wolfgang Denkff7fefe2006-03-13 12:37:35 +01001/*
2 * (C) Copyright 2003
3 * Texas Instruments <www.ti.com>
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
12 *
13 * (C) Copyright 2002-2004
Detlev Zundel792a09e2009-05-13 10:54:10 +020014 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010015 *
16 * (C) Copyright 2004
17 * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
18 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020019 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010020 */
21
22#include <common.h>
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010023
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020024#define TIMER_ENABLE (1 << 7)
25#define TIMER_MODE_MSK (1 << 6)
26#define TIMER_MODE_FR (0 << 6)
27#define TIMER_MODE_PD (1 << 6)
28
29#define TIMER_INT_EN (1 << 5)
30#define TIMER_PRS_MSK (3 << 2)
31#define TIMER_PRS_8S (1 << 3)
32#define TIMER_SIZE_MSK (1 << 2)
33#define TIMER_ONE_SHT (1 << 0)
34
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010035int timer_init (void)
36{
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020037 ulong tmr_ctrl_val;
38
39 /* 1st disable the Timer */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020041 tmr_ctrl_val &= ~TIMER_ENABLE;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020043
44 /*
45 * The Timer Control Register has one Undefined/Shouldn't Use Bit
46 * So we should do read/modify/write Operation
47 */
48
49 /*
50 * Timer Mode : Free Running
51 * Interrupt : Disabled
52 * Prescale : 8 Stage, Clk/256
53 * Tmr Siz : 16 Bit Counter
54 * Tmr in Wrapping Mode
55 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
Gururaja Hebbar K Re8f12072008-08-25 11:11:34 +020057 tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
58 tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
59
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010061
Wolfgang Denkff7fefe2006-03-13 12:37:35 +010062 return 0;
63}
64