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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
Scott Woode4c09502008-06-30 14:13:28 -05005 * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
Eran Libertyf046ccd2005-07-28 10:08:46 -05006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
28 */
29
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020030#include <asm-offsets.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050031#include <config.h>
Jon Loeligerde1d0a62005-08-01 13:20:47 -050032#include <mpc83xx.h>
Peter Tyser561858e2008-11-03 09:30:59 -060033#include <timestamp.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050034#include <version.h>
35
36#define CONFIG_83XX 1 /* needed for Linux kernel header files*/
37#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38
39#include <ppc_asm.tmpl>
40#include <ppc_defs.h>
41
42#include <asm/cache.h>
43#include <asm/mmu.h>
Peter Tyserd98b0522010-10-14 23:33:24 -050044#include <asm/u-boot.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050045
46#ifndef CONFIG_IDENT_STRING
47#define CONFIG_IDENT_STRING "MPC83XX"
48#endif
49
50/* We don't want the MMU yet.
51 */
52#undef MSR_KERNEL
53
54/*
55 * Floating Point enable, Machine Check and Recoverable Interr.
56 */
57#ifdef DEBUG
58#define MSR_KERNEL (MSR_FP|MSR_RI)
59#else
60#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61#endif
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
64#define CONFIG_SYS_FLASHBOOT
Scott Woode4c09502008-06-30 14:13:28 -050065#endif
66
Eran Libertyf046ccd2005-07-28 10:08:46 -050067/*
68 * Set up GOT: Global Offset Table
69 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +010070 * Use r12 to access the GOT
Eran Libertyf046ccd2005-07-28 10:08:46 -050071 */
72 START_GOT
73 GOT_ENTRY(_GOT2_TABLE_)
Scott Woode4c09502008-06-30 14:13:28 -050074 GOT_ENTRY(__bss_start)
75 GOT_ENTRY(_end)
Eran Libertyf046ccd2005-07-28 10:08:46 -050076
Scott Woode4c09502008-06-30 14:13:28 -050077#ifndef CONFIG_NAND_SPL
78 GOT_ENTRY(_FIXUP_TABLE_)
Eran Libertyf046ccd2005-07-28 10:08:46 -050079 GOT_ENTRY(_start)
80 GOT_ENTRY(_start_of_vectors)
81 GOT_ENTRY(_end_of_vectors)
82 GOT_ENTRY(transfer_to_handler)
Scott Woode4c09502008-06-30 14:13:28 -050083#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -050084 END_GOT
85
86/*
Jerry Van Barenf35f3582006-12-06 21:23:55 -050087 * The Hard Reset Configuration Word (HRCW) table is in the first 64
88 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
89 * times so the processor can fetch it out of flash whether the flash
90 * is 8, 16, 32, or 64 bits wide (hardware trickery).
Eran Libertyf046ccd2005-07-28 10:08:46 -050091 */
Eran Libertyf046ccd2005-07-28 10:08:46 -050092 .text
93#define _HRCW_TABLE_ENTRY(w) \
94 .fill 8,1,(((w)>>24)&0xff); \
95 .fill 8,1,(((w)>>16)&0xff); \
96 .fill 8,1,(((w)>> 8)&0xff); \
97 .fill 8,1,(((w) )&0xff)
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
100 _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500101
Jerry Van Barenf35f3582006-12-06 21:23:55 -0500102/*
103 * Magic number and version string - put it after the HRCW since it
104 * cannot be first in flash like it is in many other processors.
105 */
106 .long 0x27051956 /* U-Boot Magic Number */
107
108 .globl version_string
109version_string:
110 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600111 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
Jerry Van Barenf35f3582006-12-06 21:23:55 -0500112 .ascii " ", CONFIG_IDENT_STRING, "\0"
113
Ron Madrid455a4692008-12-12 13:12:45 -0800114 .align 2
115
116 .globl enable_addr_trans
117enable_addr_trans:
118 /* enable address translation */
119 mfmsr r5
120 ori r5, r5, (MSR_IR | MSR_DR)
121 mtmsr r5
122 isync
123 blr
124
125 .globl disable_addr_trans
126disable_addr_trans:
127 /* disable address translation */
128 mflr r4
129 mfmsr r3
130 andi. r0, r3, (MSR_IR | MSR_DR)
131 beqlr
132 andc r3, r3, r0
133 mtspr SRR0, r4
134 mtspr SRR1, r3
135 rfi
136
137 .globl get_pvr
138get_pvr:
139 mfspr r3, PVR
140 blr
141
142 .globl ppcDWstore
143ppcDWstore:
144 lfd 1, 0(r4)
145 stfd 1, 0(r3)
146 blr
147
148 .globl ppcDWload
149ppcDWload:
150 lfd 1, 0(r3)
151 stfd 1, 0(r4)
152 blr
Eran Libertyf046ccd2005-07-28 10:08:46 -0500153
Eran Libertyf046ccd2005-07-28 10:08:46 -0500154#ifndef CONFIG_DEFAULT_IMMR
155#error CONFIG_DEFAULT_IMMR must be defined
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#endif /* CONFIG_SYS_DEFAULT_IMMR */
157#ifndef CONFIG_SYS_IMMR
158#define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
159#endif /* CONFIG_SYS_IMMR */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500160
161/*
162 * After configuration, a system reset exception is executed using the
163 * vector at offset 0x100 relative to the base set by MSR[IP]. If
164 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
165 * base address is 0xfff00000. In the case of a Power On Reset or Hard
166 * Reset, the value of MSR[IP] is determined by the CIP field in the
167 * HRCW.
168 *
169 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
170 * This determines the location of the boot ROM (flash or EPROM) in the
171 * processor's address space at boot time. As long as the HRCW is set up
172 * so that we eventually end up executing the code below when the
173 * processor executes the reset exception, the actual values used should
174 * not matter.
175 *
176 * Once we have got here, the address mask in OR0 is cleared so that the
177 * bottom 32K of the boot ROM is effectively repeated all throughout the
178 * processor's address space, after which we can jump to the absolute
179 * address at which the boot ROM was linked at compile time, and proceed
180 * to initialise the memory controller without worrying if the rug will
181 * be pulled out from under us, so to speak (it will be fine as long as
182 * we configure BR0 with the same boot ROM link address).
183 */
184 . = EXC_OFF_SYS_RESET
185
186 .globl _start
187_start: /* time t 0 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500188 lis r4, CONFIG_DEFAULT_IMMR@h
189 nop
Peter Tyser52ebd9c2010-09-14 19:13:53 -0500190
Eran Libertyf046ccd2005-07-28 10:08:46 -0500191 mfmsr r5 /* save msr contents */
Scott Wood66778762009-01-20 11:56:11 -0600192
193 /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
194 bl 1f
1951: mflr r7
196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 lis r3, CONFIG_SYS_IMMR@h
198 ori r3, r3, CONFIG_SYS_IMMR@l
Scott Wood66778762009-01-20 11:56:11 -0600199
200 lwz r6, IMMRBAR(r4)
201 isync
202
Eran Libertyf046ccd2005-07-28 10:08:46 -0500203 stw r3, IMMRBAR(r4)
Scott Wood66778762009-01-20 11:56:11 -0600204 lwz r6, 0(r7) /* Arbitrary external load */
205 isync
206
207 lwz r6, IMMRBAR(r3)
208 isync
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500209
Eran Libertyf046ccd2005-07-28 10:08:46 -0500210 /* Initialise the E300 processor core */
211 /*------------------------------------------*/
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500212
Lepcha Suchitfa7b1c02008-10-16 13:38:00 -0500213#ifdef CONFIG_NAND_SPL
214 /* The FCM begins execution after only the first page
215 * is loaded. Wait for the rest before branching
216 * to another flash page.
217 */
Scott Wood66778762009-01-20 11:56:11 -06002181: lwz r6, 0x50b0(r3)
Lepcha Suchitfa7b1c02008-10-16 13:38:00 -0500219 andi. r6, r6, 1
220 beq 1b
221#endif
222
Eran Libertyf046ccd2005-07-28 10:08:46 -0500223 bl init_e300_core
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#ifdef CONFIG_SYS_FLASHBOOT
Eran Libertyf046ccd2005-07-28 10:08:46 -0500226
227 /* Inflate flash location so it appears everywhere, calculate */
228 /* the absolute address in final location of the FLASH, jump */
229 /* there and deflate the flash size back to minimal size */
230 /*------------------------------------------------------------*/
231 bl map_flash_by_law1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 lis r4, (CONFIG_SYS_MONITOR_BASE)@h
233 ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
Eran Libertyf046ccd2005-07-28 10:08:46 -0500234 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
235 mtlr r5
236 blr
237in_flash:
238#if 1 /* Remapping flash with LAW0. */
239 bl remap_flash_by_law0
240#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#endif /* CONFIG_SYS_FLASHBOOT */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500242
Kumar Gala2688e2f2006-02-10 15:40:06 -0600243 /* setup the bats */
244 bl setup_bats
245 sync
246
247 /*
248 * Cache must be enabled here for stack-in-cache trick.
249 * This means we need to enable the BATS.
250 * This means:
251 * 1) for the EVB, original gt regs need to be mapped
252 * 2) need to have an IBAT for the 0xf region,
253 * we are running there!
254 * Cache should be turned on after BATs, since by default
255 * everything is write-through.
256 * The init-mem BAT can be reused after reloc. The old
257 * gt-regs BAT can be reused after board_init_f calls
258 * board_early_init_f (EVB only).
259 */
260 /* enable address translation */
261 bl enable_addr_trans
262 sync
263
Nick Spence6eb2a442008-08-28 14:09:25 -0700264 /* enable the data cache */
Kumar Gala2688e2f2006-02-10 15:40:06 -0600265 bl dcache_enable
266 sync
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#ifdef CONFIG_SYS_INIT_RAM_LOCK
Kumar Gala2688e2f2006-02-10 15:40:06 -0600268 bl lock_ram_in_cache
269 sync
270#endif
271
272 /* set up the stack pointer in our newly created
273 * cache-ram (r1) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
275 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
Kumar Gala2688e2f2006-02-10 15:40:06 -0600276
277 li r0, 0 /* Make room for stack frame header and */
278 stwu r0, -4(r1) /* clear final stack frame so that */
279 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
280
Eran Libertyf046ccd2005-07-28 10:08:46 -0500281
282 /* let the C-code set up the rest */
Kumar Gala2688e2f2006-02-10 15:40:06 -0600283 /* */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500284 /* Be careful to keep code relocatable & stack humble */
285 /*------------------------------------------------------*/
286
287 GET_GOT /* initialize GOT access */
288
289 /* r3: IMMR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290 lis r3, CONFIG_SYS_IMMR@h
Eran Libertyf046ccd2005-07-28 10:08:46 -0500291 /* run low-level CPU init code (in Flash)*/
292 bl cpu_init_f
293
Eran Libertyf046ccd2005-07-28 10:08:46 -0500294 /* run 1st part of board init code (in Flash)*/
295 bl board_init_f
296
Peter Tyser52ebd9c2010-09-14 19:13:53 -0500297 /* NOTREACHED - board_init_f() does not return */
298
Scott Woode4c09502008-06-30 14:13:28 -0500299#ifndef CONFIG_NAND_SPL
Eran Libertyf046ccd2005-07-28 10:08:46 -0500300/*
301 * Vector Table
302 */
303
304 .globl _start_of_vectors
305_start_of_vectors:
306
307/* Machine check */
308 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
309
310/* Data Storage exception. */
311 STD_EXCEPTION(0x300, DataStorage, UnknownException)
312
313/* Instruction Storage exception. */
314 STD_EXCEPTION(0x400, InstStorage, UnknownException)
315
316/* External Interrupt exception. */
317#ifndef FIXME
318 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500319#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500320
321/* Alignment exception. */
322 . = 0x600
323Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200324 EXCEPTION_PROLOG(SRR0, SRR1)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500325 mfspr r4,DAR
326 stw r4,_DAR(r21)
327 mfspr r5,DSISR
328 stw r5,_DSISR(r21)
329 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100330 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500331
332/* Program check exception */
333 . = 0x700
334ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200335 EXCEPTION_PROLOG(SRR0, SRR1)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500336 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100337 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
338 MSR_KERNEL, COPY_EE)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500339
340 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
341
342 /* I guess we could implement decrementer, and may have
343 * to someday for timekeeping.
344 */
345 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
346
347 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
348 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
349 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
350 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
351
352 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
353 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
354
355 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
356 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
357 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
358#ifdef DEBUG
359 . = 0x1300
360 /*
361 * This exception occurs when the program counter matches the
362 * Instruction Address Breakpoint Register (IABR).
363 *
364 * I want the cpu to halt if this occurs so I can hunt around
365 * with the debugger and look at things.
366 *
367 * When DEBUG is defined, both machine check enable (in the MSR)
368 * and checkstop reset enable (in the reset mode register) are
369 * turned off and so a checkstop condition will result in the cpu
370 * halting.
371 *
372 * I force the cpu into a checkstop condition by putting an illegal
373 * instruction here (at least this is the theory).
374 *
375 * well - that didnt work, so just do an infinite loop!
376 */
3771: b 1b
378#else
379 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
380#endif
381 STD_EXCEPTION(0x1400, SMI, UnknownException)
382
383 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
384 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
385 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
386 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
387 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
388 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
389 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
390 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
391 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
392 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
393 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
394 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
395 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
396 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
397 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
398 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
399 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
400 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
401 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
402 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
403 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
404 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
405 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
406 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
407 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
408 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
409 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
410
411
412 .globl _end_of_vectors
413_end_of_vectors:
414
415 . = 0x3000
416
417/*
418 * This code finishes saving the registers to the exception frame
419 * and jumps to the appropriate handler for the exception.
420 * Register r21 is pointer into trap frame, r1 has new stack pointer.
421 */
422 .globl transfer_to_handler
423transfer_to_handler:
424 stw r22,_NIP(r21)
425 lis r22,MSR_POW@h
426 andc r23,r23,r22
427 stw r23,_MSR(r21)
428 SAVE_GPR(7, r21)
429 SAVE_4GPRS(8, r21)
430 SAVE_8GPRS(12, r21)
431 SAVE_8GPRS(24, r21)
432 mflr r23
433 andi. r24,r23,0x3f00 /* get vector offset */
434 stw r24,TRAP(r21)
435 li r22,0
436 stw r22,RESULT(r21)
437 lwz r24,0(r23) /* virtual address of handler */
438 lwz r23,4(r23) /* where to go when done */
439 mtspr SRR0,r24
440 mtspr SRR1,r20
441 mtlr r23
442 SYNC
443 rfi /* jump to handler, enable MMU */
444
445int_return:
446 mfmsr r28 /* Disable interrupts */
447 li r4,0
448 ori r4,r4,MSR_EE
449 andc r28,r28,r4
450 SYNC /* Some chip revs need this... */
451 mtmsr r28
452 SYNC
453 lwz r2,_CTR(r1)
454 lwz r0,_LINK(r1)
455 mtctr r2
456 mtlr r0
457 lwz r2,_XER(r1)
458 lwz r0,_CCR(r1)
459 mtspr XER,r2
460 mtcrf 0xFF,r0
461 REST_10GPRS(3, r1)
462 REST_10GPRS(13, r1)
463 REST_8GPRS(23, r1)
464 REST_GPR(31, r1)
465 lwz r2,_NIP(r1) /* Restore environment */
466 lwz r0,_MSR(r1)
467 mtspr SRR0,r2
468 mtspr SRR1,r0
469 lwz r0,GPR0(r1)
470 lwz r2,GPR2(r1)
471 lwz r1,GPR1(r1)
472 SYNC
473 rfi
Scott Woode4c09502008-06-30 14:13:28 -0500474#endif /* !CONFIG_NAND_SPL */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500475
476/*
477 * This code initialises the E300 processor core
478 * (conforms to PowerPC 603e spec)
479 * Note: expects original MSR contents to be in r5.
480 */
481 .globl init_e300_core
482init_e300_core: /* time t 10 */
483 /* Initialize machine status; enable machine check interrupt */
484 /*-----------------------------------------------------------*/
485
486 li r3, MSR_KERNEL /* Set ME and RI flags */
487 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
488#ifdef DEBUG
489 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
490#endif
491 SYNC /* Some chip revs need this... */
492 mtmsr r3
493 SYNC
494 mtspr SRR1, r3 /* Make SRR1 match MSR */
495
496
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497 lis r3, CONFIG_SYS_IMMR@h
Eran Libertyf046ccd2005-07-28 10:08:46 -0500498#if defined(CONFIG_WATCHDOG)
Horst Kronstorferf6970d02010-05-18 10:37:05 +0200499 /* Initialise the Watchdog values and reset it (if req) */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500500 /*------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501 lis r4, CONFIG_SYS_WATCHDOG_VALUE
Eran Libertyf046ccd2005-07-28 10:08:46 -0500502 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
503 stw r4, SWCRR(r3)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500504
Eran Libertyf046ccd2005-07-28 10:08:46 -0500505 /* and reset it */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500506
Eran Libertyf046ccd2005-07-28 10:08:46 -0500507 li r4, 0x556C
508 sth r4, SWSRR@l(r3)
Heiko Schocherf6db9452008-01-11 15:15:17 +0100509 li r4, -0x55C7
Eran Libertyf046ccd2005-07-28 10:08:46 -0500510 sth r4, SWSRR@l(r3)
511#else
Horst Kronstorferf6970d02010-05-18 10:37:05 +0200512 /* Disable Watchdog */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500513 /*-------------------*/
Kumar Galaec00c332006-01-11 11:23:01 -0600514 lwz r4, SWCRR(r3)
515 /* Check to see if its enabled for disabling
516 once disabled by SW you can't re-enable */
517 andi. r4, r4, 0x4
518 beq 1f
Eran Libertyf046ccd2005-07-28 10:08:46 -0500519 xor r4, r4, r4
520 stw r4, SWCRR(r3)
Kumar Galaec00c332006-01-11 11:23:01 -06005211:
Eran Libertyf046ccd2005-07-28 10:08:46 -0500522#endif /* CONFIG_WATCHDOG */
523
Nick Spence46497052008-08-28 14:09:19 -0700524#if defined(CONFIG_MASK_AER_AO)
525 /* Write the Arbiter Event Enable to mask Address Only traps. */
526 /* This prevents the dcbz instruction from being trapped when */
527 /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
528 /* COHERENCY bit is set in the WIMG bits, which is often */
529 /* needed for PCI operation. */
530 lwz r4, 0x0808(r3)
531 rlwinm r0, r4, 0, ~AER_AO
532 stw r0, 0x0808(r3)
533#endif /* CONFIG_MASK_AER_AO */
534
Eran Libertyf046ccd2005-07-28 10:08:46 -0500535 /* Initialize the Hardware Implementation-dependent Registers */
536 /* HID0 also contains cache control */
Nick Spence6eb2a442008-08-28 14:09:25 -0700537 /* - force invalidation of data and instruction caches */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500538 /*------------------------------------------------------*/
539
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540 lis r3, CONFIG_SYS_HID0_INIT@h
541 ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
Eran Libertyf046ccd2005-07-28 10:08:46 -0500542 SYNC
543 mtspr HID0, r3
544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545 lis r3, CONFIG_SYS_HID0_FINAL@h
546 ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
Eran Libertyf046ccd2005-07-28 10:08:46 -0500547 SYNC
548 mtspr HID0, r3
549
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200550 lis r3, CONFIG_SYS_HID2@h
551 ori r3, r3, CONFIG_SYS_HID2@l
Eran Libertyf046ccd2005-07-28 10:08:46 -0500552 SYNC
553 mtspr HID2, r3
554
Scott Woode4c09502008-06-30 14:13:28 -0500555 /* Done! */
556 /*------------------------------*/
557 blr
Eran Libertyf046ccd2005-07-28 10:08:46 -0500558
Scott Woode4c09502008-06-30 14:13:28 -0500559 /* setup_bats - set them up to some initial state */
560 .globl setup_bats
561setup_bats:
562 addis r0, r0, 0x0000
563
564 /* IBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565 addis r4, r0, CONFIG_SYS_IBAT0L@h
566 ori r4, r4, CONFIG_SYS_IBAT0L@l
567 addis r3, r0, CONFIG_SYS_IBAT0U@h
568 ori r3, r3, CONFIG_SYS_IBAT0U@l
Scott Woode4c09502008-06-30 14:13:28 -0500569 mtspr IBAT0L, r4
570 mtspr IBAT0U, r3
571
572 /* DBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573 addis r4, r0, CONFIG_SYS_DBAT0L@h
574 ori r4, r4, CONFIG_SYS_DBAT0L@l
575 addis r3, r0, CONFIG_SYS_DBAT0U@h
576 ori r3, r3, CONFIG_SYS_DBAT0U@l
Scott Woode4c09502008-06-30 14:13:28 -0500577 mtspr DBAT0L, r4
578 mtspr DBAT0U, r3
579
580 /* IBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581 addis r4, r0, CONFIG_SYS_IBAT1L@h
582 ori r4, r4, CONFIG_SYS_IBAT1L@l
583 addis r3, r0, CONFIG_SYS_IBAT1U@h
584 ori r3, r3, CONFIG_SYS_IBAT1U@l
Scott Woode4c09502008-06-30 14:13:28 -0500585 mtspr IBAT1L, r4
586 mtspr IBAT1U, r3
587
588 /* DBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589 addis r4, r0, CONFIG_SYS_DBAT1L@h
590 ori r4, r4, CONFIG_SYS_DBAT1L@l
591 addis r3, r0, CONFIG_SYS_DBAT1U@h
592 ori r3, r3, CONFIG_SYS_DBAT1U@l
Scott Woode4c09502008-06-30 14:13:28 -0500593 mtspr DBAT1L, r4
594 mtspr DBAT1U, r3
595
596 /* IBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597 addis r4, r0, CONFIG_SYS_IBAT2L@h
598 ori r4, r4, CONFIG_SYS_IBAT2L@l
599 addis r3, r0, CONFIG_SYS_IBAT2U@h
600 ori r3, r3, CONFIG_SYS_IBAT2U@l
Scott Woode4c09502008-06-30 14:13:28 -0500601 mtspr IBAT2L, r4
602 mtspr IBAT2U, r3
603
604 /* DBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200605 addis r4, r0, CONFIG_SYS_DBAT2L@h
606 ori r4, r4, CONFIG_SYS_DBAT2L@l
607 addis r3, r0, CONFIG_SYS_DBAT2U@h
608 ori r3, r3, CONFIG_SYS_DBAT2U@l
Scott Woode4c09502008-06-30 14:13:28 -0500609 mtspr DBAT2L, r4
610 mtspr DBAT2U, r3
611
612 /* IBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613 addis r4, r0, CONFIG_SYS_IBAT3L@h
614 ori r4, r4, CONFIG_SYS_IBAT3L@l
615 addis r3, r0, CONFIG_SYS_IBAT3U@h
616 ori r3, r3, CONFIG_SYS_IBAT3U@l
Scott Woode4c09502008-06-30 14:13:28 -0500617 mtspr IBAT3L, r4
618 mtspr IBAT3U, r3
619
620 /* DBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200621 addis r4, r0, CONFIG_SYS_DBAT3L@h
622 ori r4, r4, CONFIG_SYS_DBAT3L@l
623 addis r3, r0, CONFIG_SYS_DBAT3U@h
624 ori r3, r3, CONFIG_SYS_DBAT3U@l
Scott Woode4c09502008-06-30 14:13:28 -0500625 mtspr DBAT3L, r4
626 mtspr DBAT3U, r3
627
628#ifdef CONFIG_HIGH_BATS
629 /* IBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200630 addis r4, r0, CONFIG_SYS_IBAT4L@h
631 ori r4, r4, CONFIG_SYS_IBAT4L@l
632 addis r3, r0, CONFIG_SYS_IBAT4U@h
633 ori r3, r3, CONFIG_SYS_IBAT4U@l
Scott Woode4c09502008-06-30 14:13:28 -0500634 mtspr IBAT4L, r4
635 mtspr IBAT4U, r3
636
637 /* DBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200638 addis r4, r0, CONFIG_SYS_DBAT4L@h
639 ori r4, r4, CONFIG_SYS_DBAT4L@l
640 addis r3, r0, CONFIG_SYS_DBAT4U@h
641 ori r3, r3, CONFIG_SYS_DBAT4U@l
Scott Woode4c09502008-06-30 14:13:28 -0500642 mtspr DBAT4L, r4
643 mtspr DBAT4U, r3
644
645 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200646 addis r4, r0, CONFIG_SYS_IBAT5L@h
647 ori r4, r4, CONFIG_SYS_IBAT5L@l
648 addis r3, r0, CONFIG_SYS_IBAT5U@h
649 ori r3, r3, CONFIG_SYS_IBAT5U@l
Scott Woode4c09502008-06-30 14:13:28 -0500650 mtspr IBAT5L, r4
651 mtspr IBAT5U, r3
652
653 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200654 addis r4, r0, CONFIG_SYS_DBAT5L@h
655 ori r4, r4, CONFIG_SYS_DBAT5L@l
656 addis r3, r0, CONFIG_SYS_DBAT5U@h
657 ori r3, r3, CONFIG_SYS_DBAT5U@l
Scott Woode4c09502008-06-30 14:13:28 -0500658 mtspr DBAT5L, r4
659 mtspr DBAT5U, r3
660
661 /* IBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662 addis r4, r0, CONFIG_SYS_IBAT6L@h
663 ori r4, r4, CONFIG_SYS_IBAT6L@l
664 addis r3, r0, CONFIG_SYS_IBAT6U@h
665 ori r3, r3, CONFIG_SYS_IBAT6U@l
Scott Woode4c09502008-06-30 14:13:28 -0500666 mtspr IBAT6L, r4
667 mtspr IBAT6U, r3
668
669 /* DBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200670 addis r4, r0, CONFIG_SYS_DBAT6L@h
671 ori r4, r4, CONFIG_SYS_DBAT6L@l
672 addis r3, r0, CONFIG_SYS_DBAT6U@h
673 ori r3, r3, CONFIG_SYS_DBAT6U@l
Scott Woode4c09502008-06-30 14:13:28 -0500674 mtspr DBAT6L, r4
675 mtspr DBAT6U, r3
676
677 /* IBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200678 addis r4, r0, CONFIG_SYS_IBAT7L@h
679 ori r4, r4, CONFIG_SYS_IBAT7L@l
680 addis r3, r0, CONFIG_SYS_IBAT7U@h
681 ori r3, r3, CONFIG_SYS_IBAT7U@l
Scott Woode4c09502008-06-30 14:13:28 -0500682 mtspr IBAT7L, r4
683 mtspr IBAT7U, r3
684
685 /* DBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200686 addis r4, r0, CONFIG_SYS_DBAT7L@h
687 ori r4, r4, CONFIG_SYS_DBAT7L@l
688 addis r3, r0, CONFIG_SYS_DBAT7U@h
689 ori r3, r3, CONFIG_SYS_DBAT7U@l
Scott Woode4c09502008-06-30 14:13:28 -0500690 mtspr DBAT7L, r4
691 mtspr DBAT7U, r3
692#endif
693
694 isync
Eran Libertyf046ccd2005-07-28 10:08:46 -0500695
696 /* invalidate all tlb's
697 *
698 * From the 603e User Manual: "The 603e provides the ability to
699 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
700 * instruction invalidates the TLB entry indexed by the EA, and
701 * operates on both the instruction and data TLBs simultaneously
702 * invalidating four TLB entries (both sets in each TLB). The
703 * index corresponds to bits 15-19 of the EA. To invalidate all
704 * entries within both TLBs, 32 tlbie instructions should be
705 * issued, incrementing this field by one each time."
706 *
707 * "Note that the tlbia instruction is not implemented on the
708 * 603e."
709 *
710 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
711 * incrementing by 0x1000 each time. The code below is sort of
Stefan Roesea47a12b2010-04-15 16:07:28 +0200712 * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
Eran Libertyf046ccd2005-07-28 10:08:46 -0500713 *
714 */
Kumar Gala2688e2f2006-02-10 15:40:06 -0600715 lis r3, 0
716 lis r5, 2
717
7181:
719 tlbie r3
720 addi r3, r3, 0x1000
721 cmp 0, 0, r3, r5
722 blt 1b
723
724 blr
725
Eran Libertyf046ccd2005-07-28 10:08:46 -0500726/* Cache functions.
727 *
728 * Note: requires that all cache bits in
729 * HID0 are in the low half word.
730 */
Kim Phillipsa4bfc4c2010-05-14 13:18:54 -0500731#ifndef CONFIG_NAND_SPL
Eran Libertyf046ccd2005-07-28 10:08:46 -0500732 .globl icache_enable
733icache_enable:
734 mfspr r3, HID0
735 ori r3, r3, HID0_ICE
Nick Spence6eb2a442008-08-28 14:09:25 -0700736 li r4, HID0_ICFI|HID0_ILOCK
Eran Libertyf046ccd2005-07-28 10:08:46 -0500737 andc r3, r3, r4
738 ori r4, r3, HID0_ICFI
739 isync
740 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
741 isync
742 mtspr HID0, r3 /* clears invalidate */
743 blr
744
745 .globl icache_disable
746icache_disable:
747 mfspr r3, HID0
748 lis r4, 0
Nick Spence6eb2a442008-08-28 14:09:25 -0700749 ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
Eran Libertyf046ccd2005-07-28 10:08:46 -0500750 andc r3, r3, r4
Eran Libertyf046ccd2005-07-28 10:08:46 -0500751 isync
Nick Spence6eb2a442008-08-28 14:09:25 -0700752 mtspr HID0, r3 /* clears invalidate, enable and lock */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500753 blr
754
755 .globl icache_status
756icache_status:
757 mfspr r3, HID0
Marian Balakowicza7c66ad2006-03-14 16:01:25 +0100758 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
Eran Libertyf046ccd2005-07-28 10:08:46 -0500759 blr
Kim Phillipsa4bfc4c2010-05-14 13:18:54 -0500760#endif /* !CONFIG_NAND_SPL */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500761
762 .globl dcache_enable
763dcache_enable:
764 mfspr r3, HID0
Kumar Gala2688e2f2006-02-10 15:40:06 -0600765 li r5, HID0_DCFI|HID0_DLOCK
766 andc r3, r3, r5
Kumar Gala2688e2f2006-02-10 15:40:06 -0600767 ori r3, r3, HID0_DCE
Eran Libertyf046ccd2005-07-28 10:08:46 -0500768 sync
Nick Spence6eb2a442008-08-28 14:09:25 -0700769 mtspr HID0, r3 /* enable, no invalidate */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500770 blr
771
772 .globl dcache_disable
773dcache_disable:
Nick Spence6eb2a442008-08-28 14:09:25 -0700774 mflr r4
775 bl flush_dcache /* uses r3 and r5 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500776 mfspr r3, HID0
Nick Spence6eb2a442008-08-28 14:09:25 -0700777 li r5, HID0_DCE|HID0_DLOCK
778 andc r3, r3, r5
779 ori r5, r3, HID0_DCFI
Eran Libertyf046ccd2005-07-28 10:08:46 -0500780 sync
Nick Spence6eb2a442008-08-28 14:09:25 -0700781 mtspr HID0, r5 /* sets invalidate, clears enable and lock */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500782 sync
783 mtspr HID0, r3 /* clears invalidate */
Nick Spence6eb2a442008-08-28 14:09:25 -0700784 mtlr r4
Eran Libertyf046ccd2005-07-28 10:08:46 -0500785 blr
786
787 .globl dcache_status
788dcache_status:
789 mfspr r3, HID0
Marian Balakowicza7c66ad2006-03-14 16:01:25 +0100790 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
Eran Libertyf046ccd2005-07-28 10:08:46 -0500791 blr
792
Nick Spence6eb2a442008-08-28 14:09:25 -0700793 .globl flush_dcache
794flush_dcache:
795 lis r3, 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200796 lis r5, CONFIG_SYS_CACHELINE_SIZE
Nick Spence6eb2a442008-08-28 14:09:25 -07007971: cmp 0, 1, r3, r5
798 bge 2f
799 lwz r5, 0(r3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200800 lis r5, CONFIG_SYS_CACHELINE_SIZE
Nick Spence6eb2a442008-08-28 14:09:25 -0700801 addi r3, r3, 0x4
802 b 1b
8032: blr
804
Eran Libertyf046ccd2005-07-28 10:08:46 -0500805/*-------------------------------------------------------------------*/
806
807/*
808 * void relocate_code (addr_sp, gd, addr_moni)
809 *
810 * This "function" does not return, instead it continues in RAM
811 * after relocating the monitor code.
812 *
813 * r3 = dest
814 * r4 = src
815 * r5 = length in bytes
816 * r6 = cachelinesize
817 */
818 .globl relocate_code
819relocate_code:
820 mr r1, r3 /* Set new stack pointer */
821 mr r9, r4 /* Save copy of Global Data pointer */
822 mr r10, r5 /* Save copy of Destination Address */
823
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100824 GET_GOT
Eran Libertyf046ccd2005-07-28 10:08:46 -0500825 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200826 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
827 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
Scott Woode4c09502008-06-30 14:13:28 -0500828 lwz r5, GOT(__bss_start)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500829 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200830 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500831
832 /*
833 * Fix GOT pointer:
834 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200835 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500836 * + Destination Address
837 *
838 * Offset:
839 */
840 sub r15, r10, r4
841
842 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100843 add r12, r12, r15
Eran Libertyf046ccd2005-07-28 10:08:46 -0500844 /* then the one used by the C code */
845 add r30, r30, r15
846
847 /*
848 * Now relocate code
849 */
850
851 cmplw cr1,r3,r4
852 addi r0,r5,3
853 srwi. r0,r0,2
854 beq cr1,4f /* In place copy is not necessary */
855 beq 7f /* Protect against 0 count */
856 mtctr r0
857 bge cr1,2f
858 la r8,-4(r4)
859 la r7,-4(r3)
860
861 /* copy */
8621: lwzu r0,4(r8)
863 stwu r0,4(r7)
864 bdnz 1b
865
866 addi r0,r5,3
867 srwi. r0,r0,2
868 mtctr r0
869 la r8,-4(r4)
870 la r7,-4(r3)
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500871
872 /* and compare */
Eran Libertyf046ccd2005-07-28 10:08:46 -050087320: lwzu r20,4(r8)
874 lwzu r21,4(r7)
875 xor. r22, r20, r21
876 bne 30f
877 bdnz 20b
878 b 4f
879
880 /* compare failed */
88130: li r3, 0
882 blr
883
8842: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
885 add r8,r4,r0
886 add r7,r3,r0
8873: lwzu r0,-4(r8)
888 stwu r0,-4(r7)
889 bdnz 3b
Eran Libertyf046ccd2005-07-28 10:08:46 -0500890
891/*
892 * Now flush the cache: note that we must start from a cache aligned
893 * address. Otherwise we might miss one cache line.
894 */
Kumar Gala2688e2f2006-02-10 15:40:06 -06008954: cmpwi r6,0
Eran Libertyf046ccd2005-07-28 10:08:46 -0500896 add r5,r3,r5
Kumar Gala2688e2f2006-02-10 15:40:06 -0600897 beq 7f /* Always flush prefetch queue in any case */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500898 subi r0,r6,1
899 andc r3,r3,r0
Eran Libertyf046ccd2005-07-28 10:08:46 -0500900 mr r4,r3
9015: dcbst 0,r4
902 add r4,r4,r6
903 cmplw r4,r5
904 blt 5b
Kumar Gala2688e2f2006-02-10 15:40:06 -0600905 sync /* Wait for all dcbst to complete on bus */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500906 mr r4,r3
9076: icbi 0,r4
908 add r4,r4,r6
909 cmplw r4,r5
910 blt 6b
Kumar Gala2688e2f2006-02-10 15:40:06 -06009117: sync /* Wait for all icbi to complete on bus */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500912 isync
913
914/*
915 * We are done. Do not return, instead branch to second part of board
916 * initialization, now running from RAM.
917 */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500918 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
919 mtlr r0
920 blr
921
922in_ram:
923
924 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100925 * Relocation Function, r12 point to got2+0x8000
Eran Libertyf046ccd2005-07-28 10:08:46 -0500926 *
927 * Adjust got2 pointers, no need to check for 0, this code
928 * already puts a few entries in the table.
929 */
930 li r0,__got2_entries@sectoff@l
931 la r3,GOT(_GOT2_TABLE_)
932 lwz r11,GOT(_GOT2_TABLE_)
933 mtctr r0
934 sub r11,r3,r11
935 addi r3,r3,-4
9361: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200937 cmpwi r0,0
938 beq- 2f
Eran Libertyf046ccd2005-07-28 10:08:46 -0500939 add r0,r0,r11
940 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02009412: bdnz 1b
Eran Libertyf046ccd2005-07-28 10:08:46 -0500942
Scott Woode4c09502008-06-30 14:13:28 -0500943#ifndef CONFIG_NAND_SPL
Eran Libertyf046ccd2005-07-28 10:08:46 -0500944 /*
945 * Now adjust the fixups and the pointers to the fixups
946 * in case we need to move ourselves again.
947 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200948 li r0,__fixup_entries@sectoff@l
Eran Libertyf046ccd2005-07-28 10:08:46 -0500949 lwz r3,GOT(_FIXUP_TABLE_)
950 cmpwi r0,0
951 mtctr r0
952 addi r3,r3,-4
953 beq 4f
9543: lwzu r4,4(r3)
955 lwzux r0,r4,r11
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +0200956 cmpwi r0,0
Eran Libertyf046ccd2005-07-28 10:08:46 -0500957 add r0,r0,r11
Joakim Tjernlund34bbf612010-11-04 19:02:00 +0100958 stw r4,0(r3)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +0200959 beq- 5f
Eran Libertyf046ccd2005-07-28 10:08:46 -0500960 stw r0,0(r4)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +02009615: bdnz 3b
Eran Libertyf046ccd2005-07-28 10:08:46 -05009624:
Scott Woode4c09502008-06-30 14:13:28 -0500963#endif
964
Eran Libertyf046ccd2005-07-28 10:08:46 -0500965clear_bss:
966 /*
967 * Now clear BSS segment
968 */
969 lwz r3,GOT(__bss_start)
970#if defined(CONFIG_HYMOD)
971 /*
972 * For HYMOD - the environment is the very last item in flash.
973 * The real .bss stops just before environment starts, so only
974 * clear up to that point.
975 *
976 * taken from mods for FADS board
977 */
978 lwz r4,GOT(environment)
979#else
980 lwz r4,GOT(_end)
981#endif
982
983 cmplw 0, r3, r4
984 beq 6f
985
986 li r0, 0
9875:
988 stw r0, 0(r3)
989 addi r3, r3, 4
990 cmplw 0, r3, r4
991 bne 5b
9926:
993
994 mr r3, r9 /* Global Data pointer */
995 mr r4, r10 /* Destination Address */
996 bl board_init_r
997
Scott Woode4c09502008-06-30 14:13:28 -0500998#ifndef CONFIG_NAND_SPL
Eran Libertyf046ccd2005-07-28 10:08:46 -0500999 /*
1000 * Copy exception vector code to low memory
1001 *
1002 * r3: dest_addr
1003 * r7: source address, r8: end address, r9: target address
1004 */
1005 .globl trap_init
1006trap_init:
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001007 mflr r4 /* save link register */
1008 GET_GOT
Eran Libertyf046ccd2005-07-28 10:08:46 -05001009 lwz r7, GOT(_start)
1010 lwz r8, GOT(_end_of_vectors)
1011
1012 li r9, 0x100 /* reset vector always at 0x100 */
1013
1014 cmplw 0, r7, r8
1015 bgelr /* return if r7>=r8 - just in case */
Eran Libertyf046ccd2005-07-28 10:08:46 -050010161:
1017 lwz r0, 0(r7)
1018 stw r0, 0(r9)
1019 addi r7, r7, 4
1020 addi r9, r9, 4
1021 cmplw 0, r7, r8
1022 bne 1b
1023
1024 /*
1025 * relocate `hdlr' and `int_return' entries
1026 */
1027 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1028 li r8, Alignment - _start + EXC_OFF_SYS_RESET
10292:
1030 bl trap_reloc
1031 addi r7, r7, 0x100 /* next exception vector */
1032 cmplw 0, r7, r8
1033 blt 2b
1034
1035 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1036 bl trap_reloc
1037
1038 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1039 bl trap_reloc
1040
1041 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1042 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
10433:
1044 bl trap_reloc
1045 addi r7, r7, 0x100 /* next exception vector */
1046 cmplw 0, r7, r8
1047 blt 3b
1048
1049 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1050 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
10514:
1052 bl trap_reloc
1053 addi r7, r7, 0x100 /* next exception vector */
1054 cmplw 0, r7, r8
1055 blt 4b
1056
1057 mfmsr r3 /* now that the vectors have */
1058 lis r7, MSR_IP@h /* relocated into low memory */
1059 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1060 andc r3, r3, r7 /* (if it was on) */
1061 SYNC /* Some chip revs need this... */
1062 mtmsr r3
1063 SYNC
1064
1065 mtlr r4 /* restore link register */
1066 blr
1067
Scott Woode4c09502008-06-30 14:13:28 -05001068#endif /* !CONFIG_NAND_SPL */
Eran Libertyf046ccd2005-07-28 10:08:46 -05001069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001070#ifdef CONFIG_SYS_INIT_RAM_LOCK
Kumar Gala2688e2f2006-02-10 15:40:06 -06001071lock_ram_in_cache:
1072 /* Allocate Initial RAM in data cache.
1073 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001074 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1075 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk553f0982010-10-26 13:32:32 +02001076 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001077 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spenceade50c72008-08-28 14:09:11 -07001078 mtctr r4
Kumar Gala2688e2f2006-02-10 15:40:06 -060010791:
1080 dcbz r0, r3
1081 addi r3, r3, 32
1082 bdnz 1b
1083
1084 /* Lock the data cache */
1085 mfspr r0, HID0
Nick Spence6eb2a442008-08-28 14:09:25 -07001086 ori r0, r0, HID0_DLOCK
Kumar Gala2688e2f2006-02-10 15:40:06 -06001087 sync
1088 mtspr HID0, r0
1089 sync
1090 blr
1091
Scott Woode4c09502008-06-30 14:13:28 -05001092#ifndef CONFIG_NAND_SPL
Eran Libertyf046ccd2005-07-28 10:08:46 -05001093.globl unlock_ram_in_cache
1094unlock_ram_in_cache:
1095 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001096 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
1097 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk553f0982010-10-26 13:32:32 +02001098 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001099 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spenceade50c72008-08-28 14:09:11 -07001100 mtctr r4
Eran Libertyf046ccd2005-07-28 10:08:46 -050011011: icbi r0, r3
1102 dcbi r0, r3
1103 addi r3, r3, 32
1104 bdnz 1b
1105 sync /* Wait for all icbi to complete on bus */
1106 isync
Kumar Gala2688e2f2006-02-10 15:40:06 -06001107
1108 /* Unlock the data cache and invalidate it */
1109 mfspr r3, HID0
1110 li r5, HID0_DLOCK|HID0_DCFI
1111 andc r3, r3, r5 /* no invalidate, unlock */
1112 ori r5, r3, HID0_DCFI /* invalidate, unlock */
Kumar Gala2688e2f2006-02-10 15:40:06 -06001113 sync
Nick Spence6eb2a442008-08-28 14:09:25 -07001114 mtspr HID0, r5 /* invalidate, unlock */
1115 sync
1116 mtspr HID0, r3 /* no invalidate, unlock */
Eran Libertyf046ccd2005-07-28 10:08:46 -05001117 blr
Scott Woode4c09502008-06-30 14:13:28 -05001118#endif /* !CONFIG_NAND_SPL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001119#endif /* CONFIG_SYS_INIT_RAM_LOCK */
Eran Libertyf046ccd2005-07-28 10:08:46 -05001120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001121#ifdef CONFIG_SYS_FLASHBOOT
Eran Libertyf046ccd2005-07-28 10:08:46 -05001122map_flash_by_law1:
1123 /* When booting from ROM (Flash or EPROM), clear the */
1124 /* Address Mask in OR0 so ROM appears everywhere */
1125 /*----------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001126 lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001127 lwz r4, OR0@l(r3)
Eran Libertyf046ccd2005-07-28 10:08:46 -05001128 li r5, 0x7fff /* r5 <= 0x00007FFFF */
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001129 and r4, r4, r5
Eran Libertyf046ccd2005-07-28 10:08:46 -05001130 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1131
1132 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1133 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1134 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1135 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1136 * 0xFF800. From the hard resetting to here, the processor fetched and
1137 * executed the instructions one by one. There is not absolutely
1138 * jumping happened. Laterly, the u-boot code has to do an absolutely
1139 * jumping to tell the CPU instruction fetching component what the
1140 * u-boot TEXT base address is. Because the TEXT base resides in the
1141 * boot ROM memory space, to garantee the code can run smoothly after
1142 * that jumping, we must map in the entire boot ROM by Local Access
1143 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1144 * address for boot ROM, such as 0xFE000000. In this case, the default
1145 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1146 * need another window to map in it.
1147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001148 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1149 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1150 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
Timur Tabi31068b72006-08-22 17:07:00 -05001151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001152 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
Timur Tabi31068b72006-08-22 17:07:00 -05001153 lis r4, (0x80000012)@h
1154 ori r4, r4, (0x80000012)@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001155 li r5, CONFIG_SYS_FLASH_SIZE
Timur Tabi31068b72006-08-22 17:07:00 -050011561: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1157 addi r4, r4, 1
1158 bne 1b
1159
Eran Libertyf046ccd2005-07-28 10:08:46 -05001160 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
Joakim Tjernlunde45c98a2010-11-19 14:15:33 +01001161 /* Wait for HW to catch up */
1162 lwz r4, LBLAWAR1(r3)
1163 twi 0,r4,0
1164 isync
Eran Libertyf046ccd2005-07-28 10:08:46 -05001165 blr
1166
1167 /* Though all the LBIU Local Access Windows and LBC Banks will be
1168 * initialized in the C code, we'd better configure boot ROM's
1169 * window 0 and bank 0 correctly at here.
1170 */
1171remap_flash_by_law0:
1172 /* Initialize the BR0 with the boot ROM starting address. */
1173 lwz r4, BR0(r3)
1174 li r5, 0x7FFF
Jon Loeligerde1d0a62005-08-01 13:20:47 -05001175 and r4, r4, r5
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001176 lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
1177 ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
Eran Libertyf046ccd2005-07-28 10:08:46 -05001178 or r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001179 stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
Eran Libertyf046ccd2005-07-28 10:08:46 -05001180
1181 lwz r4, OR0(r3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001182 lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
Eran Libertyf046ccd2005-07-28 10:08:46 -05001183 or r4, r4, r5
Timur Tabi31068b72006-08-22 17:07:00 -05001184 stw r4, OR0(r3)
Eran Libertyf046ccd2005-07-28 10:08:46 -05001185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001186 lis r4, (CONFIG_SYS_FLASH_BASE)@h
1187 ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
1188 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
Eran Libertyf046ccd2005-07-28 10:08:46 -05001189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001190 /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
Timur Tabi31068b72006-08-22 17:07:00 -05001191 lis r4, (0x80000012)@h
1192 ori r4, r4, (0x80000012)@l
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001193 li r5, CONFIG_SYS_FLASH_SIZE
Timur Tabi31068b72006-08-22 17:07:00 -050011941: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1195 addi r4, r4, 1
1196 bne 1b
1197 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1198
Eran Libertyf046ccd2005-07-28 10:08:46 -05001199
1200 xor r4, r4, r4
1201 stw r4, LBLAWBAR1(r3)
1202 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
Joakim Tjernlunde45c98a2010-11-19 14:15:33 +01001203 /* Wait for HW to catch up */
1204 lwz r4, LBLAWAR1(r3)
1205 twi 0,r4,0
1206 isync
Eran Libertyf046ccd2005-07-28 10:08:46 -05001207 blr
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001208#endif /* CONFIG_SYS_FLASHBOOT */