blob: 53e8d05f50b1a251484e8be719ab216350e1c6b5 [file] [log] [blame]
wdenk416fef12002-05-15 20:05:05 +00001/*
2 * include/asm-ppc/cache.h
3 */
4#ifndef __ARCH_PPC_CACHE_H
5#define __ARCH_PPC_CACHE_H
6
7#include <linux/config.h>
8#include <asm/processor.h>
9
10/* bytes per L1 cache line */
Kumar Galab009f3e2008-01-08 01:22:21 -060011#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
12#define L1_CACHE_SHIFT 4
13#elif defined(CONFIG_PPC64BRIDGE)
Stefan Roese9b94ac62007-10-31 17:55:58 +010014#define L1_CACHE_SHIFT 7
Kumar Gala0f060c32008-10-23 01:47:38 -050015#elif defined(CONFIG_E500MC)
16#define L1_CACHE_SHIFT 6
wdenk416fef12002-05-15 20:05:05 +000017#else
Stefan Roese9b94ac62007-10-31 17:55:58 +010018#define L1_CACHE_SHIFT 5
Kumar Galab009f3e2008-01-08 01:22:21 -060019#endif
Stefan Roese9b94ac62007-10-31 17:55:58 +010020
21#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
22
23/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
Stefan Roese9b94ac62007-10-31 17:55:58 +010025 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#ifndef CONFIG_SYS_CACHELINE_SIZE
27#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
Stefan Roese9b94ac62007-10-31 17:55:58 +010028#endif
wdenk416fef12002-05-15 20:05:05 +000029
30#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
31#define L1_CACHE_PAGES 8
32
33#define SMP_CACHE_BYTES L1_CACHE_BYTES
34
35#ifdef MODULE
36#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
37#else
38#define __cacheline_aligned \
39 __attribute__((__aligned__(L1_CACHE_BYTES), \
40 __section__(".data.cacheline_aligned")))
41#endif
42
43#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
44extern void flush_dcache_range(unsigned long start, unsigned long stop);
45extern void clean_dcache_range(unsigned long start, unsigned long stop);
46extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
Stefan Roese9b94ac62007-10-31 17:55:58 +010047extern void flush_dcache(void);
48extern void invalidate_dcache(void);
Kumar Gala54e091d2008-09-22 14:11:10 -050049extern void invalidate_icache(void);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#ifdef CONFIG_SYS_INIT_RAM_LOCK
wdenk416fef12002-05-15 20:05:05 +000051extern void unlock_ram_in_cache(void);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#endif /* CONFIG_SYS_INIT_RAM_LOCK */
wdenk416fef12002-05-15 20:05:05 +000053#endif /* __ASSEMBLY__ */
54
55/* prep registers for L2 */
56#define CACHECRBA 0x80000823 /* Cache configuration register address */
57#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
58#define L2CACHE_512KB 0x00 /* 512KB */
59#define L2CACHE_256KB 0x01 /* 256KB */
60#define L2CACHE_1MB 0x02 /* 1MB */
61#define L2CACHE_NONE 0x03 /* NONE */
62#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
63
64#ifdef CONFIG_8xx
65/* Cache control on the MPC8xx is provided through some additional
66 * special purpose registers.
67 */
68#define IC_CST 560 /* Instruction cache control/status */
69#define IC_ADR 561 /* Address needed for some commands */
70#define IC_DAT 562 /* Read-only data register */
71#define DC_CST 568 /* Data cache control/status */
72#define DC_ADR 569 /* Address needed for some commands */
73#define DC_DAT 570 /* Read-only data register */
74
75/* Commands. Only the first few are available to the instruction cache.
76*/
77#define IDC_ENABLE 0x02000000 /* Cache enable */
78#define IDC_DISABLE 0x04000000 /* Cache disable */
79#define IDC_LDLCK 0x06000000 /* Load and lock */
80#define IDC_UNLINE 0x08000000 /* Unlock line */
81#define IDC_UNALL 0x0a000000 /* Unlock all */
82#define IDC_INVALL 0x0c000000 /* Invalidate all */
83
84#define DC_FLINE 0x0e000000 /* Flush data cache line */
85#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
86#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
87#define DC_SLES 0x05000000 /* Set little endian swap mode */
88#define DC_CLES 0x07000000 /* Clear little endian swap mode */
89
90/* Status.
91*/
92#define IDC_ENABLED 0x80000000 /* Cache is enabled */
93#define IDC_CERR1 0x00200000 /* Cache error 1 */
94#define IDC_CERR2 0x00100000 /* Cache error 2 */
95#define IDC_CERR3 0x00080000 /* Cache error 3 */
96
97#define DC_DFWT 0x40000000 /* Data cache is forced write through */
98#define DC_LES 0x20000000 /* Caches are little endian mode */
99#endif /* CONFIG_8xx */
100
101#endif