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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Vivek Mahajan4ef01012009-05-25 17:23:16 +05302 * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
Jon Loeligerde1d0a62005-08-01 13:20:47 -05003 *
Dave Liuf6eda7f2006-10-25 14:41:21 -05004 * MPC83xx Internal Memory Map
5 *
Dave Liue0803132006-12-07 21:11:58 +08006 * Contributors:
7 * Dave Liu <daveliu@freescale.com>
8 * Tanya Jiang <tanya.jiang@freescale.com>
9 * Mandy Lavi <mandy.lavi@freescale.com>
10 * Eran Liberty <liberty@freescale.com>
Dave Liuf6eda7f2006-10-25 14:41:21 -050011 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Dave Liue0803132006-12-07 21:11:58 +080019 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Dave Liuf6eda7f2006-10-25 14:41:21 -050020 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
Eran Libertyf046ccd2005-07-28 10:08:46 -050027 */
Dave Liuf6eda7f2006-10-25 14:41:21 -050028#ifndef __IMMAP_83xx__
29#define __IMMAP_83xx__
Eran Libertyf046ccd2005-07-28 10:08:46 -050030
31#include <asm/types.h>
Timur Tabibe5e6182006-11-03 19:15:00 -060032#include <asm/fsl_i2c.h>
Ben Warren04a9e112008-01-16 22:37:35 -050033#include <asm/mpc8xxx_spi.h>
Haiying Wang4e190b02008-10-29 11:05:55 -040034#include <asm/fsl_lbc.h>
Peter Tysere94e4602009-06-30 17:15:51 -050035#include <asm/fsl_dma.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050036
Jon Loeligerde1d0a62005-08-01 13:20:47 -050037/*
Dave Liue0803132006-12-07 21:11:58 +080038 * Local Access Window
Eran Libertyf046ccd2005-07-28 10:08:46 -050039 */
Dave Liuf6eda7f2006-10-25 14:41:21 -050040typedef struct law83xx {
Dave Liub7016522006-10-31 19:25:38 -060041 u32 bar; /* LBIU local access window base address register */
Dave Liub7016522006-10-31 19:25:38 -060042 u32 ar; /* LBIU local access window attribute register */
Dave Liuf6eda7f2006-10-25 14:41:21 -050043} law83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -050044
Jon Loeligerde1d0a62005-08-01 13:20:47 -050045/*
Dave Liue0803132006-12-07 21:11:58 +080046 * System configuration registers
Eran Libertyf046ccd2005-07-28 10:08:46 -050047 */
Dave Liuf6eda7f2006-10-25 14:41:21 -050048typedef struct sysconf83xx {
Dave Liub7016522006-10-31 19:25:38 -060049 u32 immrbar; /* Internal memory map base address register */
Eran Libertyf046ccd2005-07-28 10:08:46 -050050 u8 res0[0x04];
Dave Liub7016522006-10-31 19:25:38 -060051 u32 altcbar; /* Alternate configuration base address register */
Eran Libertyf046ccd2005-07-28 10:08:46 -050052 u8 res1[0x14];
Dave Liub7016522006-10-31 19:25:38 -060053 law83xx_t lblaw[4]; /* LBIU local access window */
Eran Libertyf046ccd2005-07-28 10:08:46 -050054 u8 res2[0x20];
Dave Liub7016522006-10-31 19:25:38 -060055 law83xx_t pcilaw[2]; /* PCI local access window */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030056 u8 res3[0x10];
57 law83xx_t pcielaw[2]; /* PCI Express local access window */
58 u8 res4[0x10];
Dave Liub7016522006-10-31 19:25:38 -060059 law83xx_t ddrlaw[2]; /* DDR local access window */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030060 u8 res5[0x50];
Dave Liub7016522006-10-31 19:25:38 -060061 u32 sgprl; /* System General Purpose Register Low */
62 u32 sgprh; /* System General Purpose Register High */
63 u32 spridr; /* System Part and Revision ID Register */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030064 u8 res6[0x04];
Dave Liub7016522006-10-31 19:25:38 -060065 u32 spcr; /* System Priority Configuration Register */
Dave Liue0803132006-12-07 21:11:58 +080066 u32 sicrl; /* System I/O Configuration Register Low */
67 u32 sicrh; /* System I/O Configuration Register High */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030068 u8 res7[0x04];
Nick Spence002d27c2008-08-22 23:52:40 -070069 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
70 u32 sidcr1; /* System I/O Delay Configuration Register 1 */
Dave Liu24c3aca2006-12-07 21:13:15 +080071 u32 ddrcdr; /* DDR Control Driver Register */
72 u32 ddrdsr; /* DDR Debug Status Register */
Dave Liu03051c32007-09-18 12:36:11 +080073 u32 obir; /* Output Buffer Impedance Register */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +030074 u8 res8[0xC];
75 u32 pecr1; /* PCI Express control register 1 */
76 u32 pecr2; /* PCI Express control register 2 */
77 u8 res9[0xB8];
Dave Liuf6eda7f2006-10-25 14:41:21 -050078} sysconf83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -050079
Jon Loeligerde1d0a62005-08-01 13:20:47 -050080/*
Eran Libertyf046ccd2005-07-28 10:08:46 -050081 * Watch Dog Timer (WDT) Registers
82 */
Dave Liuf6eda7f2006-10-25 14:41:21 -050083typedef struct wdt83xx {
Jon Loeligerde1d0a62005-08-01 13:20:47 -050084 u8 res0[4];
Dave Liub7016522006-10-31 19:25:38 -060085 u32 swcrr; /* System watchdog control register */
86 u32 swcnr; /* System watchdog count register */
Jon Loeligerde1d0a62005-08-01 13:20:47 -050087 u8 res1[2];
Dave Liub7016522006-10-31 19:25:38 -060088 u16 swsrr; /* System watchdog service register */
Eran Libertyf046ccd2005-07-28 10:08:46 -050089 u8 res2[0xF0];
Dave Liuf6eda7f2006-10-25 14:41:21 -050090} wdt83xx_t;
Jon Loeligerde1d0a62005-08-01 13:20:47 -050091
Eran Libertyf046ccd2005-07-28 10:08:46 -050092/*
93 * RTC/PIT Module Registers
94 */
Dave Liuf6eda7f2006-10-25 14:41:21 -050095typedef struct rtclk83xx {
Dave Liub7016522006-10-31 19:25:38 -060096 u32 cnr; /* control register */
Dave Liub7016522006-10-31 19:25:38 -060097 u32 ldr; /* load register */
Dave Liub7016522006-10-31 19:25:38 -060098 u32 psr; /* prescale register */
Dave Liue0803132006-12-07 21:11:58 +080099 u32 ctr; /* counter value field register */
Dave Liub7016522006-10-31 19:25:38 -0600100 u32 evr; /* event register */
Dave Liub7016522006-10-31 19:25:38 -0600101 u32 alr; /* alarm register */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500102 u8 res0[0xE8];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500103} rtclk83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500104
105/*
Dave Liue0803132006-12-07 21:11:58 +0800106 * Global timer module
Eran Libertyf046ccd2005-07-28 10:08:46 -0500107 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500108typedef struct gtm83xx {
Dave Liue0803132006-12-07 21:11:58 +0800109 u8 cfr1; /* Timer1/2 Configuration */
Dave Liub7016522006-10-31 19:25:38 -0600110 u8 res0[3];
Dave Liue0803132006-12-07 21:11:58 +0800111 u8 cfr2; /* Timer3/4 Configuration */
Dave Liub7016522006-10-31 19:25:38 -0600112 u8 res1[10];
Dave Liue0803132006-12-07 21:11:58 +0800113 u16 mdr1; /* Timer1 Mode Register */
114 u16 mdr2; /* Timer2 Mode Register */
115 u16 rfr1; /* Timer1 Reference Register */
116 u16 rfr2; /* Timer2 Reference Register */
117 u16 cpr1; /* Timer1 Capture Register */
118 u16 cpr2; /* Timer2 Capture Register */
119 u16 cnr1; /* Timer1 Counter Register */
120 u16 cnr2; /* Timer2 Counter Register */
121 u16 mdr3; /* Timer3 Mode Register */
122 u16 mdr4; /* Timer4 Mode Register */
123 u16 rfr3; /* Timer3 Reference Register */
124 u16 rfr4; /* Timer4 Reference Register */
125 u16 cpr3; /* Timer3 Capture Register */
126 u16 cpr4; /* Timer4 Capture Register */
127 u16 cnr3; /* Timer3 Counter Register */
128 u16 cnr4; /* Timer4 Counter Register */
129 u16 evr1; /* Timer1 Event Register */
130 u16 evr2; /* Timer2 Event Register */
131 u16 evr3; /* Timer3 Event Register */
132 u16 evr4; /* Timer4 Event Register */
133 u16 psr1; /* Timer1 Prescaler Register */
134 u16 psr2; /* Timer2 Prescaler Register */
135 u16 psr3; /* Timer3 Prescaler Register */
136 u16 psr4; /* Timer4 Prescaler Register */
Dave Liub7016522006-10-31 19:25:38 -0600137 u8 res[0xC0];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500138} gtm83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500139
140/*
141 * Integrated Programmable Interrupt Controller
142 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500143typedef struct ipic83xx {
Dave Liue0803132006-12-07 21:11:58 +0800144 u32 sicfr; /* System Global Interrupt Configuration Register */
145 u32 sivcr; /* System Global Interrupt Vector Register */
146 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
147 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
148 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
Dave Liub7016522006-10-31 19:25:38 -0600149 u8 res0[8];
Dave Liue0803132006-12-07 21:11:58 +0800150 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
151 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
152 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
Dave Liub7016522006-10-31 19:25:38 -0600153 u8 res1[4];
Dave Liue0803132006-12-07 21:11:58 +0800154 u32 sepnr; /* System External Interrupt Pending Register */
155 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
156 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
157 u32 semsr; /* System External Interrupt Mask Register */
158 u32 secnr; /* System External Interrupt Control Register */
159 u32 sersr; /* System Error Status Register */
160 u32 sermr; /* System Error Mask Register */
161 u32 sercr; /* System Error Control Register */
Dave Liub7016522006-10-31 19:25:38 -0600162 u8 res2[4];
Dave Liue0803132006-12-07 21:11:58 +0800163 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
164 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
165 u32 sefcr; /* System External Interrupt Force Register */
166 u32 serfr; /* System Error Force Register */
Dave Liub7016522006-10-31 19:25:38 -0600167 u32 scvcr; /* System Critical Interrupt Vector Register */
Dave Liub7016522006-10-31 19:25:38 -0600168 u32 smvcr; /* System Management Interrupt Vector Register */
Dave Liub7016522006-10-31 19:25:38 -0600169 u8 res3[0x98];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500170} ipic83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500171
172/*
173 * System Arbiter Registers
174 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500175typedef struct arbiter83xx {
Dave Liub7016522006-10-31 19:25:38 -0600176 u32 acr; /* Arbiter Configuration Register */
Dave Liub7016522006-10-31 19:25:38 -0600177 u32 atr; /* Arbiter Timers Register */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500178 u8 res[4];
Dave Liue0803132006-12-07 21:11:58 +0800179 u32 aer; /* Arbiter Event Register */
180 u32 aidr; /* Arbiter Interrupt Definition Register */
181 u32 amr; /* Arbiter Mask Register */
Dave Liub7016522006-10-31 19:25:38 -0600182 u32 aeatr; /* Arbiter Event Attributes Register */
Dave Liub7016522006-10-31 19:25:38 -0600183 u32 aeadr; /* Arbiter Event Address Register */
Dave Liue0803132006-12-07 21:11:58 +0800184 u32 aerr; /* Arbiter Event Response Register */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500185 u8 res1[0xDC];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500186} arbiter83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500187
188/*
189 * Reset Module
190 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500191typedef struct reset83xx {
Dave Liue0803132006-12-07 21:11:58 +0800192 u32 rcwl; /* Reset Configuration Word Low Register */
193 u32 rcwh; /* Reset Configuration Word High Register */
Dave Liub7016522006-10-31 19:25:38 -0600194 u8 res0[8];
Dave Liue0803132006-12-07 21:11:58 +0800195 u32 rsr; /* Reset Status Register */
196 u32 rmr; /* Reset Mode Register */
197 u32 rpr; /* Reset protection Register */
198 u32 rcr; /* Reset Control Register */
199 u32 rcer; /* Reset Control Enable Register */
Dave Liub7016522006-10-31 19:25:38 -0600200 u8 res1[0xDC];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500201} reset83xx_t;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500202
Dave Liue0803132006-12-07 21:11:58 +0800203/*
204 * Clock Module
205 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500206typedef struct clk83xx {
Dave Liue0803132006-12-07 21:11:58 +0800207 u32 spmr; /* system PLL mode Register */
208 u32 occr; /* output clock control Register */
209 u32 sccr; /* system clock control Register */
Dave Liub7016522006-10-31 19:25:38 -0600210 u8 res0[0xF4];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500211} clk83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500212
213/*
214 * Power Management Control Module
215 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500216typedef struct pmc83xx {
Dave Liue0803132006-12-07 21:11:58 +0800217 u32 pmccr; /* PMC Configuration Register */
218 u32 pmcer; /* PMC Event Register */
219 u32 pmcmr; /* PMC Mask Register */
Scott Woodd87c57b2007-04-16 14:31:55 -0500220 u32 pmccr1; /* PMC Configuration Register 1 */
221 u32 pmccr2; /* PMC Configuration Register 2 */
222 u8 res0[0xEC];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500223} pmc83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500224
225/*
Dave Liue0803132006-12-07 21:11:58 +0800226 * General purpose I/O module
Eran Libertyf046ccd2005-07-28 10:08:46 -0500227 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500228typedef struct gpio83xx {
Dave Liub7016522006-10-31 19:25:38 -0600229 u32 dir; /* direction register */
230 u32 odr; /* open drain register */
231 u32 dat; /* data register */
232 u32 ier; /* interrupt event register */
233 u32 imr; /* interrupt mask register */
234 u32 icr; /* external interrupt control register */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500235 u8 res0[0xE8];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500236} gpio83xx_t;
Dave Liub7016522006-10-31 19:25:38 -0600237
Dave Liub7016522006-10-31 19:25:38 -0600238/*
239 * QE Ports Interrupts Registers
240 */
241typedef struct qepi83xx {
242 u8 res0[0xC];
243 u32 qepier; /* QE Ports Interrupt Event Register */
Dave Liub7016522006-10-31 19:25:38 -0600244 u32 qepimr; /* QE Ports Interrupt Mask Register */
Dave Liub7016522006-10-31 19:25:38 -0600245 u32 qepicr; /* QE Ports Interrupt Control Register */
Dave Liub7016522006-10-31 19:25:38 -0600246 u8 res1[0xE8];
247} qepi83xx_t;
248
249/*
Dave Liue0803132006-12-07 21:11:58 +0800250 * QE Parallel I/O Ports
Dave Liub7016522006-10-31 19:25:38 -0600251 */
252typedef struct gpio_n {
253 u32 podr; /* Open Drain Register */
254 u32 pdat; /* Data Register */
255 u32 dir1; /* direction register 1 */
256 u32 dir2; /* direction register 2 */
257 u32 ppar1; /* Pin Assignment Register 1 */
258 u32 ppar2; /* Pin Assignment Register 2 */
259} gpio_n_t;
260
Dave Liue0803132006-12-07 21:11:58 +0800261typedef struct qegpio83xx {
Dave Liub7016522006-10-31 19:25:38 -0600262 gpio_n_t ioport[0x7];
263 u8 res0[0x358];
Dave Liue0803132006-12-07 21:11:58 +0800264} qepio83xx_t;
Dave Liub7016522006-10-31 19:25:38 -0600265
266/*
267 * QE Secondary Bus Access Windows
268 */
Dave Liub7016522006-10-31 19:25:38 -0600269typedef struct qesba83xx {
270 u32 lbmcsar; /* Local bus memory controller start address */
Dave Liub7016522006-10-31 19:25:38 -0600271 u32 sdmcsar; /* Secondary DDR memory controller start address */
Dave Liub7016522006-10-31 19:25:38 -0600272 u8 res0[0x38];
273 u32 lbmcear; /* Local bus memory controller end address */
Dave Liub7016522006-10-31 19:25:38 -0600274 u32 sdmcear; /* Secondary DDR memory controller end address */
Dave Liub7016522006-10-31 19:25:38 -0600275 u8 res1[0x38];
Dave Liue0803132006-12-07 21:11:58 +0800276 u32 lbmcar; /* Local bus memory controller attributes */
Dave Liub7016522006-10-31 19:25:38 -0600277 u32 sdmcar; /* Secondary DDR memory controller attributes */
Dave Liue0803132006-12-07 21:11:58 +0800278 u8 res2[0x378];
Dave Liub7016522006-10-31 19:25:38 -0600279} qesba83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500280
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500281/*
Eran Libertyf046ccd2005-07-28 10:08:46 -0500282 * DDR Memory Controller Memory Map
283 */
Dave Liub7016522006-10-31 19:25:38 -0600284typedef struct ddr_cs_bnds {
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500285 u32 csbnds;
Dave Liub7016522006-10-31 19:25:38 -0600286 u8 res0[4];
Eran Libertyf046ccd2005-07-28 10:08:46 -0500287} ddr_cs_bnds_t;
288
Dave Liuf6eda7f2006-10-25 14:41:21 -0500289typedef struct ddr83xx {
Dave Liue0803132006-12-07 21:11:58 +0800290 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500291 u8 res0[0x60];
Dave Liue0803132006-12-07 21:11:58 +0800292 u32 cs_config[4]; /* Chip Select x Configuration */
Dave Liu24c3aca2006-12-07 21:13:15 +0800293 u8 res1[0x70];
294 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
295 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
Dave Liue0803132006-12-07 21:11:58 +0800296 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
297 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
298 u32 sdram_cfg; /* SDRAM Control Configuration */
Dave Liu24c3aca2006-12-07 21:13:15 +0800299 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
Dave Liue0803132006-12-07 21:11:58 +0800300 u32 sdram_mode; /* SDRAM Mode Configuration */
Dave Liu24c3aca2006-12-07 21:13:15 +0800301 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
302 u32 sdram_md_cntl; /* SDRAM Mode Control */
Dave Liue0803132006-12-07 21:11:58 +0800303 u32 sdram_interval; /* SDRAM Interval Configuration */
Dave Liu24c3aca2006-12-07 21:13:15 +0800304 u32 ddr_data_init; /* SDRAM Data Initialization */
305 u8 res2[4];
306 u32 sdram_clk_cntl; /* SDRAM Clock Control */
307 u8 res3[0x14];
308 u32 ddr_init_addr; /* DDR training initialization address */
309 u32 ddr_init_ext_addr; /* DDR training initialization extended address */
310 u8 res4[0xAA8];
311 u32 ddr_ip_rev1; /* DDR IP block revision 1 */
312 u32 ddr_ip_rev2; /* DDR IP block revision 2 */
313 u8 res5[0x200];
Dave Liue0803132006-12-07 21:11:58 +0800314 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
315 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
316 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
Dave Liu24c3aca2006-12-07 21:13:15 +0800317 u8 res6[0x14];
Dave Liue0803132006-12-07 21:11:58 +0800318 u32 capture_data_hi; /* Memory Data Path Read Capture High */
319 u32 capture_data_lo; /* Memory Data Path Read Capture Low */
320 u32 capture_ecc; /* Memory Data Path Read Capture ECC */
Dave Liu24c3aca2006-12-07 21:13:15 +0800321 u8 res7[0x14];
Dave Liue0803132006-12-07 21:11:58 +0800322 u32 err_detect; /* Memory Error Detect */
323 u32 err_disable; /* Memory Error Disable */
324 u32 err_int_en; /* Memory Error Interrupt Enable */
325 u32 capture_attributes; /* Memory Error Attributes Capture */
326 u32 capture_address; /* Memory Error Address Capture */
327 u32 capture_ext_address;/* Memory Error Extended Address Capture */
328 u32 err_sbe; /* Memory Single-Bit ECC Error Management */
Dave Liu24c3aca2006-12-07 21:13:15 +0800329 u8 res8[0xA4];
Eran Libertyf046ccd2005-07-28 10:08:46 -0500330 u32 debug_reg;
Dave Liu24c3aca2006-12-07 21:13:15 +0800331 u8 res9[0xFC];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500332} ddr83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500333
334/*
Eran Libertyf046ccd2005-07-28 10:08:46 -0500335 * DUART
336 */
Dave Liub7016522006-10-31 19:25:38 -0600337typedef struct duart83xx {
Dave Liue0803132006-12-07 21:11:58 +0800338 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
339 u8 uier_udmb; /* combined register for UIER and UDMB */
340 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
341 u8 ulcr; /* line control register */
342 u8 umcr; /* MODEM control register */
343 u8 ulsr; /* line status register */
344 u8 umsr; /* MODEM status register */
345 u8 uscr; /* scratch register */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500346 u8 res0[8];
Dave Liue0803132006-12-07 21:11:58 +0800347 u8 udsr; /* DMA status register */
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500348 u8 res1[3];
349 u8 res2[0xEC];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500350} duart83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500351
352/*
Marian Balakowicz61f25152006-03-14 16:14:48 +0100353 * DMA/Messaging Unit
354 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500355typedef struct dma83xx {
Dave Liub7016522006-10-31 19:25:38 -0600356 u32 res0[0xC]; /* 0x0-0x29 reseverd */
357 u32 omisr; /* 0x30 Outbound message interrupt status register */
358 u32 omimr; /* 0x34 Outbound message interrupt mask register */
359 u32 res1[0x6]; /* 0x38-0x49 reserved */
Dave Liub7016522006-10-31 19:25:38 -0600360 u32 imr0; /* 0x50 Inbound message register 0 */
361 u32 imr1; /* 0x54 Inbound message register 1 */
362 u32 omr0; /* 0x58 Outbound message register 0 */
363 u32 omr1; /* 0x5C Outbound message register 1 */
Dave Liub7016522006-10-31 19:25:38 -0600364 u32 odr; /* 0x60 Outbound doorbell register */
365 u32 res2; /* 0x64-0x67 reserved */
366 u32 idr; /* 0x68 Inbound doorbell register */
367 u32 res3[0x5]; /* 0x6C-0x79 reserved */
Dave Liub7016522006-10-31 19:25:38 -0600368 u32 imisr; /* 0x80 Inbound message interrupt status register */
369 u32 imimr; /* 0x84 Inbound message interrupt mask register */
370 u32 res4[0x1E]; /* 0x88-0x99 reserved */
Peter Tysere94e4602009-06-30 17:15:51 -0500371 struct fsl_dma dma[4];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500372} dma83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500373
374/*
375 * PCI Software Configuration Registers
376 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500377typedef struct pciconf83xx {
Dave Liub7016522006-10-31 19:25:38 -0600378 u32 config_address;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500379 u32 config_data;
380 u32 int_ack;
Dave Liub7016522006-10-31 19:25:38 -0600381 u8 res[116];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500382} pciconf83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500383
384/*
385 * PCI Outbound Translation Register
386 */
387typedef struct pci_outbound_window {
Dave Liub7016522006-10-31 19:25:38 -0600388 u32 potar;
389 u8 res0[4];
390 u32 pobar;
391 u8 res1[4];
392 u32 pocmr;
393 u8 res2[4];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500394} pot83xx_t;
Dave Liub7016522006-10-31 19:25:38 -0600395
Eran Libertyf046ccd2005-07-28 10:08:46 -0500396/*
397 * Sequencer
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500398 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500399typedef struct ios83xx {
Dave Liub7016522006-10-31 19:25:38 -0600400 pot83xx_t pot[6];
Dave Liub7016522006-10-31 19:25:38 -0600401 u8 res0[0x60];
402 u32 pmcr;
403 u8 res1[4];
404 u32 dtcr;
405 u8 res2[4];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500406} ios83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500407
408/*
409 * PCI Controller Control and Status Registers
410 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500411typedef struct pcictrl83xx {
Dave Liub7016522006-10-31 19:25:38 -0600412 u32 esr;
Dave Liub7016522006-10-31 19:25:38 -0600413 u32 ecdr;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500414 u32 eer;
Dave Liub7016522006-10-31 19:25:38 -0600415 u32 eatcr;
Dave Liub7016522006-10-31 19:25:38 -0600416 u32 eacr;
417 u32 eeacr;
Dave Liub7016522006-10-31 19:25:38 -0600418 u32 edlcr;
419 u32 edhcr;
Dave Liub7016522006-10-31 19:25:38 -0600420 u32 gcr;
421 u32 ecr;
422 u32 gsr;
423 u8 res0[12];
424 u32 pitar2;
425 u8 res1[4];
426 u32 pibar2;
427 u32 piebar2;
428 u32 piwar2;
429 u8 res2[4];
430 u32 pitar1;
431 u8 res3[4];
432 u32 pibar1;
433 u32 piebar1;
434 u32 piwar1;
435 u8 res4[4];
436 u32 pitar0;
437 u8 res5[4];
438 u32 pibar0;
439 u8 res6[4];
440 u32 piwar0;
441 u8 res7[132];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500442} pcictrl83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500443
444/*
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500445 * USB
Eran Libertyf046ccd2005-07-28 10:08:46 -0500446 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500447typedef struct usb83xx {
Scott Woodd87c57b2007-04-16 14:31:55 -0500448 u8 fixme[0x1000];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500449} usb83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500450
451/*
452 * TSEC
453 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500454typedef struct tsec83xx {
Eran Libertyf046ccd2005-07-28 10:08:46 -0500455 u8 fixme[0x1000];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500456} tsec83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500457
458/*
459 * Security
460 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500461typedef struct security83xx {
Eran Libertyf046ccd2005-07-28 10:08:46 -0500462 u8 fixme[0x10000];
Dave Liuf6eda7f2006-10-25 14:41:21 -0500463} security83xx_t;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500464
Dave Liu03051c32007-09-18 12:36:11 +0800465/*
466 * PCI Express
467 */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300468struct pex_inbound_window {
469 u32 ar;
470 u32 tar;
471 u32 barl;
472 u32 barh;
473};
474
475struct pex_outbound_window {
476 u32 ar;
477 u32 bar;
478 u32 tarl;
479 u32 tarh;
480};
481
482struct pex_csb_bridge {
483 u32 pex_csb_ver;
484 u32 pex_csb_cab;
485 u32 pex_csb_ctrl;
486 u8 res0[8];
487 u32 pex_dms_dstmr;
488 u8 res1[4];
489 u32 pex_cbs_stat;
490 u8 res2[0x20];
491 u32 pex_csb_obctrl;
492 u32 pex_csb_obstat;
493 u8 res3[0x98];
494 u32 pex_csb_ibctrl;
495 u32 pex_csb_ibstat;
496 u8 res4[0xb8];
497 u32 pex_wdma_ctrl;
498 u32 pex_wdma_addr;
499 u32 pex_wdma_stat;
500 u8 res5[0x94];
501 u32 pex_rdma_ctrl;
502 u32 pex_rdma_addr;
503 u32 pex_rdma_stat;
504 u8 res6[0xd4];
505 u32 pex_ombcr;
506 u32 pex_ombdr;
507 u8 res7[0x38];
508 u32 pex_imbcr;
509 u32 pex_imbdr;
510 u8 res8[0x38];
511 u32 pex_int_enb;
512 u32 pex_int_stat;
513 u32 pex_int_apio_vec1;
514 u32 pex_int_apio_vec2;
515 u8 res9[0x10];
516 u32 pex_int_ppio_vec1;
517 u32 pex_int_ppio_vec2;
518 u32 pex_int_wdma_vec1;
519 u32 pex_int_wdma_vec2;
520 u32 pex_int_rdma_vec1;
521 u32 pex_int_rdma_vec2;
522 u32 pex_int_misc_vec;
523 u8 res10[4];
524 u32 pex_int_axi_pio_enb;
525 u32 pex_int_axi_wdma_enb;
526 u32 pex_int_axi_rdma_enb;
527 u32 pex_int_axi_misc_enb;
528 u32 pex_int_axi_pio_stat;
529 u32 pex_int_axi_wdma_stat;
530 u32 pex_int_axi_rdma_stat;
531 u32 pex_int_axi_misc_stat;
532 u8 res11[0xa0];
533 struct pex_outbound_window pex_outbound_win[4];
534 u8 res12[0x100];
535 u32 pex_epiwtar0;
536 u32 pex_epiwtar1;
537 u32 pex_epiwtar2;
538 u32 pex_epiwtar3;
539 u8 res13[0x70];
540 struct pex_inbound_window pex_inbound_win[4];
541};
542
Dave Liu03051c32007-09-18 12:36:11 +0800543typedef struct pex83xx {
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300544 u8 pex_cfg_header[0x404];
545 u32 pex_ltssm_stat;
546 u8 res0[0x30];
547 u32 pex_ack_replay_timeout;
548 u8 res1[4];
549 u32 pex_gclk_ratio;
550 u8 res2[0xc];
551 u32 pex_pm_timer;
552 u32 pex_pme_timeout;
553 u8 res3[4];
554 u32 pex_aspm_req_timer;
555 u8 res4[0x18];
556 u32 pex_ssvid_update;
557 u8 res5[0x34];
558 u32 pex_cfg_ready;
559 u8 res6[0x24];
560 u32 pex_bar_sizel;
561 u8 res7[4];
562 u32 pex_bar_sel;
563 u8 res8[0x20];
564 u32 pex_bar_pf;
565 u8 res9[0x88];
566 u32 pex_pme_to_ack_tor;
567 u8 res10[0xc];
568 u32 pex_ss_intr_mask;
569 u8 res11[0x25c];
570 struct pex_csb_bridge bridge;
571 u8 res12[0x160];
Dave Liu03051c32007-09-18 12:36:11 +0800572} pex83xx_t;
573
574/*
575 * SATA
576 */
577typedef struct sata83xx {
578 u8 fixme[0x1000];
579} sata83xx_t;
580
581/*
582 * eSDHC
583 */
584typedef struct sdhc83xx {
585 u8 fixme[0x1000];
586} sdhc83xx_t;
587
588/*
589 * SerDes
590 */
591typedef struct serdes83xx {
592 u8 fixme[0x100];
593} serdes83xx_t;
594
595/*
596 * On Chip ROM
597 */
598typedef struct rom83xx {
599 u8 mem[0x10000];
600} rom83xx_t;
601
Dave Liu555da612007-09-18 12:36:58 +0800602/*
603 * TDM
604 */
605typedef struct tdm83xx {
606 u8 fixme[0x200];
607} tdm83xx_t;
608
609/*
610 * TDM DMAC
611 */
612typedef struct tdmdmac83xx {
613 u8 fixme[0x2000];
614} tdmdmac83xx_t;
615
Peter Tyser2c7920a2009-05-22 17:23:25 -0500616#if defined(CONFIG_MPC834x)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500617typedef struct immap {
Dave Liue0803132006-12-07 21:11:58 +0800618 sysconf83xx_t sysconf; /* System configuration */
619 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
620 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
621 rtclk83xx_t pit; /* Periodic Interval Timer */
622 gtm83xx_t gtm[2]; /* Global Timers Module */
623 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
624 arbiter83xx_t arbiter; /* System Arbiter Registers */
625 reset83xx_t reset; /* Reset Module */
626 clk83xx_t clk; /* System Clock Module */
627 pmc83xx_t pmc; /* Power Management Control Module */
628 gpio83xx_t gpio[2]; /* General purpose I/O module */
629 u8 res0[0x200];
630 u8 dll_ddr[0x100];
631 u8 dll_lbc[0x100];
632 u8 res1[0xE00];
633 ddr83xx_t ddr; /* DDR Memory Controller Memory */
634 fsl_i2c_t i2c[2]; /* I2C Controllers */
635 u8 res2[0x1300];
636 duart83xx_t duart[2]; /* DUART */
637 u8 res3[0x900];
Haiying Wang4e190b02008-10-29 11:05:55 -0400638 fsl_lbus_t lbus; /* Local Bus Controller Registers */
Dave Liue0803132006-12-07 21:11:58 +0800639 u8 res4[0x1000];
Ben Warren04a9e112008-01-16 22:37:35 -0500640 spi8xxx_t spi; /* Serial Peripheral Interface */
Dave Liue0803132006-12-07 21:11:58 +0800641 dma83xx_t dma; /* DMA */
642 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
643 ios83xx_t ios; /* Sequencer */
644 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
645 u8 res5[0x19900];
Scott Woodd87c57b2007-04-16 14:31:55 -0500646 usb83xx_t usb[2];
647 tsec83xx_t tsec[2];
648 u8 res6[0xA000];
649 security83xx_t security;
650 u8 res7[0xC0000];
651} immap_t;
652
Valeriy Glushkovd89e1c32009-06-30 15:48:40 +0300653#ifdef CONFIG_HAS_FSL_MPH_USB
654#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x22000 /* use the MPH controller */
655#else
656#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000 /* use the DR controller */
657#endif
658
Dave Liu555da612007-09-18 12:36:58 +0800659#elif defined(CONFIG_MPC8313)
Scott Woodd87c57b2007-04-16 14:31:55 -0500660typedef struct immap {
661 sysconf83xx_t sysconf; /* System configuration */
662 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
663 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
664 rtclk83xx_t pit; /* Periodic Interval Timer */
665 gtm83xx_t gtm[2]; /* Global Timers Module */
666 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
667 arbiter83xx_t arbiter; /* System Arbiter Registers */
668 reset83xx_t reset; /* Reset Module */
669 clk83xx_t clk; /* System Clock Module */
670 pmc83xx_t pmc; /* Power Management Control Module */
671 gpio83xx_t gpio[1]; /* General purpose I/O module */
672 u8 res0[0x1300];
673 ddr83xx_t ddr; /* DDR Memory Controller Memory */
674 fsl_i2c_t i2c[2]; /* I2C Controllers */
675 u8 res1[0x1300];
676 duart83xx_t duart[2]; /* DUART */
677 u8 res2[0x900];
Haiying Wang4e190b02008-10-29 11:05:55 -0400678 fsl_lbus_t lbus; /* Local Bus Controller Registers */
Scott Woodd87c57b2007-04-16 14:31:55 -0500679 u8 res3[0x1000];
Ben Warren04a9e112008-01-16 22:37:35 -0500680 spi8xxx_t spi; /* Serial Peripheral Interface */
Scott Woodd87c57b2007-04-16 14:31:55 -0500681 dma83xx_t dma; /* DMA */
682 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
683 u8 res4[0x80];
684 ios83xx_t ios; /* Sequencer */
685 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
686 u8 res5[0x1aa00];
687 usb83xx_t usb[1];
Dave Liue0803132006-12-07 21:11:58 +0800688 tsec83xx_t tsec[2];
689 u8 res6[0xA000];
690 security83xx_t security;
691 u8 res7[0xC0000];
Eran Libertyf046ccd2005-07-28 10:08:46 -0500692} immap_t;
693
Dave Liu555da612007-09-18 12:36:58 +0800694#elif defined(CONFIG_MPC8315)
695typedef struct immap {
696 sysconf83xx_t sysconf; /* System configuration */
697 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
698 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
699 rtclk83xx_t pit; /* Periodic Interval Timer */
700 gtm83xx_t gtm[2]; /* Global Timers Module */
701 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
702 arbiter83xx_t arbiter; /* System Arbiter Registers */
703 reset83xx_t reset; /* Reset Module */
704 clk83xx_t clk; /* System Clock Module */
705 pmc83xx_t pmc; /* Power Management Control Module */
706 gpio83xx_t gpio[1]; /* General purpose I/O module */
707 u8 res0[0x1300];
708 ddr83xx_t ddr; /* DDR Memory Controller Memory */
709 fsl_i2c_t i2c[2]; /* I2C Controllers */
710 u8 res1[0x1300];
711 duart83xx_t duart[2]; /* DUART */
712 u8 res2[0x900];
Haiying Wang4e190b02008-10-29 11:05:55 -0400713 fsl_lbus_t lbus; /* Local Bus Controller Registers */
Dave Liu555da612007-09-18 12:36:58 +0800714 u8 res3[0x1000];
Ben Warren04a9e112008-01-16 22:37:35 -0500715 spi8xxx_t spi; /* Serial Peripheral Interface */
Dave Liu555da612007-09-18 12:36:58 +0800716 dma83xx_t dma; /* DMA */
717 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
718 u8 res4[0x80];
719 ios83xx_t ios; /* Sequencer */
720 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
721 u8 res5[0xa00];
722 pex83xx_t pciexp[2]; /* PCI Express Controller */
723 u8 res6[0xb000];
724 tdm83xx_t tdm; /* TDM Controller */
725 u8 res7[0x1e00];
726 sata83xx_t sata[2]; /* SATA Controller */
727 u8 res8[0x9000];
728 usb83xx_t usb[1]; /* USB DR Controller */
729 tsec83xx_t tsec[2];
730 u8 res9[0x6000];
731 tdmdmac83xx_t tdmdmac; /* TDM DMAC */
732 u8 res10[0x2000];
733 security83xx_t security;
734 u8 res11[0xA3000];
735 serdes83xx_t serdes[1]; /* SerDes Registers */
736 u8 res12[0x1CF00];
737} immap_t;
738
Peter Tyser2c7920a2009-05-22 17:23:25 -0500739#elif defined(CONFIG_MPC837x)
Dave Liu03051c32007-09-18 12:36:11 +0800740typedef struct immap {
741 sysconf83xx_t sysconf; /* System configuration */
742 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
743 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
744 rtclk83xx_t pit; /* Periodic Interval Timer */
745 gtm83xx_t gtm[2]; /* Global Timers Module */
746 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
747 arbiter83xx_t arbiter; /* System Arbiter Registers */
748 reset83xx_t reset; /* Reset Module */
749 clk83xx_t clk; /* System Clock Module */
750 pmc83xx_t pmc; /* Power Management Control Module */
751 gpio83xx_t gpio[2]; /* General purpose I/O module */
752 u8 res0[0x1200];
753 ddr83xx_t ddr; /* DDR Memory Controller Memory */
754 fsl_i2c_t i2c[2]; /* I2C Controllers */
755 u8 res1[0x1300];
756 duart83xx_t duart[2]; /* DUART */
757 u8 res2[0x900];
Haiying Wang4e190b02008-10-29 11:05:55 -0400758 fsl_lbus_t lbus; /* Local Bus Controller Registers */
Dave Liu03051c32007-09-18 12:36:11 +0800759 u8 res3[0x1000];
Ben Warren04a9e112008-01-16 22:37:35 -0500760 spi8xxx_t spi; /* Serial Peripheral Interface */
Dave Liu03051c32007-09-18 12:36:11 +0800761 dma83xx_t dma; /* DMA */
762 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
763 u8 res4[0x80];
764 ios83xx_t ios; /* Sequencer */
765 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
766 u8 res5[0xa00];
767 pex83xx_t pciexp[2]; /* PCI Express Controller */
768 u8 res6[0xd000];
769 sata83xx_t sata[4]; /* SATA Controller */
770 u8 res7[0x7000];
771 usb83xx_t usb[1]; /* USB DR Controller */
772 tsec83xx_t tsec[2];
773 u8 res8[0x8000];
774 sdhc83xx_t sdhc; /* SDHC Controller */
775 u8 res9[0x1000];
776 security83xx_t security;
777 u8 res10[0xA3000];
778 serdes83xx_t serdes[2]; /* SerDes Registers */
779 u8 res11[0xCE00];
780 rom83xx_t rom; /* On Chip ROM */
781} immap_t;
782
Dave Liue0803132006-12-07 21:11:58 +0800783#elif defined(CONFIG_MPC8360)
784typedef struct immap {
785 sysconf83xx_t sysconf; /* System configuration */
786 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
787 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
788 rtclk83xx_t pit; /* Periodic Interval Timer */
789 u8 res0[0x200];
790 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
791 arbiter83xx_t arbiter; /* System Arbiter Registers */
792 reset83xx_t reset; /* Reset Module */
793 clk83xx_t clk; /* System Clock Module */
794 pmc83xx_t pmc; /* Power Management Control Module */
795 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
796 u8 res1[0x300];
797 u8 dll_ddr[0x100];
798 u8 dll_lbc[0x100];
799 u8 res2[0x200];
800 qepio83xx_t qepio; /* QE Parallel I/O ports */
801 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
802 u8 res3[0x400];
803 ddr83xx_t ddr; /* DDR Memory Controller Memory */
804 fsl_i2c_t i2c[2]; /* I2C Controllers */
805 u8 res4[0x1300];
806 duart83xx_t duart[2]; /* DUART */
807 u8 res5[0x900];
Haiying Wang4e190b02008-10-29 11:05:55 -0400808 fsl_lbus_t lbus; /* Local Bus Controller Registers */
Dave Liue0803132006-12-07 21:11:58 +0800809 u8 res6[0x2000];
810 dma83xx_t dma; /* DMA */
811 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
812 u8 res7[128];
813 ios83xx_t ios; /* Sequencer (IOS) */
814 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
815 u8 res8[0x4A00];
816 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
817 u8 res9[0x22000];
818 security83xx_t security;
819 u8 res10[0xC0000];
820 u8 qe[0x100000]; /* QE block */
821} immap_t;
Dave Liu24c3aca2006-12-07 21:13:15 +0800822
Peter Tyser2c7920a2009-05-22 17:23:25 -0500823#elif defined(CONFIG_MPC832x)
Dave Liu24c3aca2006-12-07 21:13:15 +0800824typedef struct immap {
825 sysconf83xx_t sysconf; /* System configuration */
826 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
827 rtclk83xx_t rtc; /* Real Time Clock Module Registers */
828 rtclk83xx_t pit; /* Periodic Interval Timer */
829 gtm83xx_t gtm[2]; /* Global Timers Module */
830 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
831 arbiter83xx_t arbiter; /* System Arbiter Registers */
832 reset83xx_t reset; /* Reset Module */
833 clk83xx_t clk; /* System Clock Module */
834 pmc83xx_t pmc; /* Power Management Control Module */
835 qepi83xx_t qepi; /* QE Ports Interrupts Registers */
836 u8 res0[0x300];
837 u8 dll_ddr[0x100];
838 u8 dll_lbc[0x100];
839 u8 res1[0x200];
840 qepio83xx_t qepio; /* QE Parallel I/O ports */
841 u8 res2[0x800];
842 ddr83xx_t ddr; /* DDR Memory Controller Memory */
843 fsl_i2c_t i2c[2]; /* I2C Controllers */
844 u8 res3[0x1300];
845 duart83xx_t duart[2]; /* DUART */
846 u8 res4[0x900];
Haiying Wang4e190b02008-10-29 11:05:55 -0400847 fsl_lbus_t lbus; /* Local Bus Controller Registers */
Dave Liu24c3aca2006-12-07 21:13:15 +0800848 u8 res5[0x2000];
849 dma83xx_t dma; /* DMA */
850 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
851 u8 res6[128];
852 ios83xx_t ios; /* Sequencer (IOS) */
853 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
854 u8 res7[0x27A00];
855 security83xx_t security;
856 u8 res8[0xC0000];
857 u8 qe[0x100000]; /* QE block */
858} immap_t;
Dave Liue0803132006-12-07 21:11:58 +0800859#endif
860
Peter Tysere94e4602009-06-30 17:15:51 -0500861#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
862#define CONFIG_SYS_MPC83xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
Andy Fleminge1ac3872008-10-30 16:50:14 -0500863#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000)
864#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
Valeriy Glushkovd89e1c32009-06-30 15:48:40 +0300865
866#ifndef CONFIG_SYS_MPC83xx_USB_OFFSET
867#define CONFIG_SYS_MPC83xx_USB_OFFSET 0x23000
868#endif
Vivek Mahajan4ef01012009-05-25 17:23:16 +0530869#define CONFIG_SYS_MPC83xx_USB_ADDR \
870 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
Dave Liub7016522006-10-31 19:25:38 -0600871#endif /* __IMMAP_83xx__ */