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wdenk2abbe072003-06-16 23:50:08 +00001/*
wdenk8bde7f72003-06-27 21:31:46 +00002 * NOTE: DAVICOM ethernet Physical layer
wdenk2abbe072003-06-16 23:50:08 +00003 *
4 * Version: @(#)DM9161.h 1.0.0 01/10/2001
5 *
6 * Authors: ATMEL Rousset
7 *
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15
wdenk8bde7f72003-06-27 21:31:46 +000016/* DAVICOM PHYSICAL LAYER TRANSCEIVER DM9161 */
wdenk2abbe072003-06-16 23:50:08 +000017
Wolfgang Denk53677ef2008-05-20 16:00:29 +020018#define DM9161_BMCR 0 /* Basic Mode Control Register */
wdenk8bde7f72003-06-27 21:31:46 +000019#define DM9161_BMSR 1 /* Basic Mode Status Register */
20#define DM9161_PHYID1 2 /* PHY Idendifier Register 1 */
21#define DM9161_PHYID2 3 /* PHY Idendifier Register 2 */
22#define DM9161_ANAR 4 /* Auto_Negotiation Advertisement Register */
23#define DM9161_ANLPAR 5 /* Auto_negotiation Link Partner Ability Register */
24#define DM9161_ANER 6 /* Auto-negotiation Expansion Register */
25#define DM9161_DSCR 16 /* Specified Configuration Register */
26#define DM9161_DSCSR 17 /* Specified Configuration and Status Register */
27#define DM9161_10BTCSR 18 /* 10BASE-T Configuration and Satus Register */
28#define DM9161_MDINTR 21 /* Specified Interrupt Register */
29#define DM9161_RECR 22 /* Specified Receive Error Counter Register */
30#define DM9161_DISCR 23 /* Specified Disconnect Counter Register */
31#define DM9161_RLSR 24 /* Hardware Reset Latch State Register */
wdenk2abbe072003-06-16 23:50:08 +000032
33
wdenk8bde7f72003-06-27 21:31:46 +000034/* --Bit definitions: DM9161_BMCR */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020035#define DM9161_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
wdenk8bde7f72003-06-27 21:31:46 +000036#define DM9161_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
37#define DM9161_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
wdenk2abbe072003-06-16 23:50:08 +000038#define DM9161_AUTONEG (1 << 12)
39#define DM9161_POWER_DOWN (1 << 11)
wdenk8bde7f72003-06-27 21:31:46 +000040#define DM9161_ISOLATE (1 << 10)
wdenk2abbe072003-06-16 23:50:08 +000041#define DM9161_RESTART_AUTONEG (1 << 9)
42#define DM9161_DUPLEX_MODE (1 << 8)
43#define DM9161_COLLISION_TEST (1 << 7)
44
wdenk8bde7f72003-06-27 21:31:46 +000045/*--Bit definitions: DM9161_BMSR */
Peter Pearsed4fc6012007-08-14 10:10:52 +010046#define DM9161_100BASE_TX (1 << 15)
wdenk2abbe072003-06-16 23:50:08 +000047#define DM9161_100BASE_TX_FD (1 << 14)
Peter Pearsed4fc6012007-08-14 10:10:52 +010048#define DM9161_100BASE_TX_HD (1 << 13)
wdenk2abbe072003-06-16 23:50:08 +000049#define DM9161_10BASE_T_FD (1 << 12)
50#define DM9161_10BASE_T_HD (1 << 11)
51#define DM9161_MF_PREAMB_SUPPR (1 << 6)
52#define DM9161_AUTONEG_COMP (1 << 5)
53#define DM9161_REMOTE_FAULT (1 << 4)
54#define DM9161_AUTONEG_ABILITY (1 << 3)
55#define DM9161_LINK_STATUS (1 << 2)
56#define DM9161_JABBER_DETECT (1 << 1)
57#define DM9161_EXTEND_CAPAB (1 << 0)
58
wdenk8bde7f72003-06-27 21:31:46 +000059/*--definitions: DM9161_PHYID1 */
wdenk2abbe072003-06-16 23:50:08 +000060#define DM9161_PHYID1_OUI 0x606E
61#define DM9161_LSB_MASK 0x3F
62
wdenk8bde7f72003-06-27 21:31:46 +000063/*--Bit definitions: DM9161_ANAR, DM9161_ANLPAR */
wdenk2abbe072003-06-16 23:50:08 +000064#define DM9161_NP (1 << 15)
65#define DM9161_ACK (1 << 14)
66#define DM9161_RF (1 << 13)
67#define DM9161_FCS (1 << 10)
68#define DM9161_T4 (1 << 9)
69#define DM9161_TX_FDX (1 << 8)
70#define DM9161_TX_HDX (1 << 7)
71#define DM9161_10_FDX (1 << 6)
72#define DM9161_10_HDX (1 << 5)
73#define DM9161_AN_IEEE_802_3 0x0001
74
wdenk8bde7f72003-06-27 21:31:46 +000075/*--Bit definitions: DM9161_ANER */
wdenk2abbe072003-06-16 23:50:08 +000076#define DM9161_PDF (1 << 4)
77#define DM9161_LP_NP_ABLE (1 << 3)
78#define DM9161_NP_ABLE (1 << 2)
79#define DM9161_PAGE_RX (1 << 1)
80#define DM9161_LP_AN_ABLE (1 << 0)
81
wdenk8bde7f72003-06-27 21:31:46 +000082/*--Bit definitions: DM9161_DSCR */
wdenk2abbe072003-06-16 23:50:08 +000083#define DM9161_BP4B5B (1 << 15)
84#define DM9161_BP_SCR (1 << 14)
85#define DM9161_BP_ALIGN (1 << 13)
86#define DM9161_BP_ADPOK (1 << 12)
87#define DM9161_REPEATER (1 << 11)
88#define DM9161_TX (1 << 10)
89#define DM9161_RMII_ENABLE (1 << 8)
90#define DM9161_F_LINK_100 (1 << 7)
91#define DM9161_SPLED_CTL (1 << 6)
92#define DM9161_COLLED_CTL (1 << 5)
93#define DM9161_RPDCTR_EN (1 << 4)
94#define DM9161_SM_RST (1 << 3)
95#define DM9161_MFP SC (1 << 2)
96#define DM9161_SLEEP (1 << 1)
97#define DM9161_RLOUT (1 << 0)
98
wdenk8bde7f72003-06-27 21:31:46 +000099/*--Bit definitions: DM9161_DSCSR */
wdenk2abbe072003-06-16 23:50:08 +0000100#define DM9161_100FDX (1 << 15)
101#define DM9161_100HDX (1 << 14)
102#define DM9161_10FDX (1 << 13)
103#define DM9161_10HDX (1 << 12)
104
wdenk8bde7f72003-06-27 21:31:46 +0000105/*--Bit definitions: DM9161_10BTCSR */
wdenk2abbe072003-06-16 23:50:08 +0000106#define DM9161_LP_EN (1 << 14)
107#define DM9161_HBE (1 << 13)
108#define DM9161_SQUELCH (1 << 12)
109#define DM9161_JABEN (1 << 11)
110#define DM9161_10BT_SER (1 << 10)
111#define DM9161_POLR (1 << 0)
112
113
wdenk8bde7f72003-06-27 21:31:46 +0000114/*--Bit definitions: DM9161_MDINTR */
wdenk2abbe072003-06-16 23:50:08 +0000115#define DM9161_INTR_PEND (1 << 15)
116#define DM9161_FDX_MASK (1 << 11)
117#define DM9161_SPD_MASK (1 << 10)
118#define DM9161_LINK_MASK (1 << 9)
119#define DM9161_INTR_MASK (1 << 8)
120#define DM9161_FDX_CHANGE (1 << 4)
121#define DM9161_SPD_CHANGE (1 << 3)
122#define DM9161_LINK_CHANGE (1 << 2)
123#define DM9161_INTR_STATUS (1 << 0)
124
125
126/****************** function prototypes **********************/
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200127unsigned int dm9161_IsPhyConnected(AT91PS_EMAC p_mac);
128unsigned char dm9161_GetLinkSpeed(AT91PS_EMAC p_mac);
129unsigned char dm9161_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
130unsigned char dm9161_InitPhy(AT91PS_EMAC p_mac);