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wdenkc7de8292002-11-19 11:04:11 +00001/*
2 * (C) Copyright 2001
3 * Denis Peter, MPL AG Switzerland
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Note: Part of this code has been derived from linux
24 *
25 */
26#ifndef _USB_UHCI_H_
27#define _USB_UHCI_H_
28
29#undef USB_UHCI_VEND_ID
30#define USB_UHCI_VEND_ID PCI_VENDOR_ID_VIA
31#undef USB_UHCI_DEV_ID
32#define USB_UHCI_DEV_ID 0x3038
33
34/* Command register */
35#define USBCMD 0
36#define USBCMD_RS 0x0001 /* Run/Stop */
37#define USBCMD_HCRESET 0x0002 /* Host reset */
38#define USBCMD_GRESET 0x0004 /* Global reset */
39#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
40#define USBCMD_FGR 0x0010 /* Force Global Resume */
41#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
42#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
43#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
44
45/* Status register */
46#define USBSTS 2
47#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
48#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
49#define USBSTS_RD 0x0004 /* Resume Detect */
50#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
51#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
52#define USBSTS_HCH 0x0020 /* HC Halted */
53
54/* Interrupt enable register */
55#define USBINTR 4
56#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
57#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
58#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
59#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
60
61#define USBFRNUM 6
62#define USBFLBASEADD 8
63#define USBSOF 12
64
65/* USB port status and control registers */
66#define USBPORTSC1 16
67#define USBPORTSC2 18
68#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
69#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
70#define USBPORTSC_PE 0x0004 /* Port Enable */
71#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
72#define USBPORTSC_LS 0x0030 /* Line Status */
73#define USBPORTSC_RD 0x0040 /* Resume Detect */
74#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
75#define USBPORTSC_PR 0x0200 /* Port Reset */
76#define USBPORTSC_SUSP 0x1000 /* Suspend */
77
78/* Legacy support register */
79#define USBLEGSUP 0xc0
80#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
81
82#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */
83#define UHCI_PID 0xff /* PID MASK */
84
85#define UHCI_PTR_BITS 0x000F
86#define UHCI_PTR_TERM 0x0001
87#define UHCI_PTR_QH 0x0002
88#define UHCI_PTR_DEPTH 0x0004
89
90/* for TD <status>: */
91#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
92#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
93#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
94#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
95#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
96#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
97#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
98#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
99#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
100#define TD_CTRL_NAK (1 << 19) /* NAK Received */
101#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
102#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
103#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */
104
105#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
106 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
107
108#define TD_TOKEN_TOGGLE 19
109
110/* ------------------------------------------------------------------------------------
111 Virtual Root HUB
112 ------------------------------------------------------------------------------------ */
113/* destination of request */
114#define RH_INTERFACE 0x01
115#define RH_ENDPOINT 0x02
116#define RH_OTHER 0x03
117
118#define RH_CLASS 0x20
119#define RH_VENDOR 0x40
120
121/* Requests: bRequest << 8 | bmRequestType */
122#define RH_GET_STATUS 0x0080
123#define RH_CLEAR_FEATURE 0x0100
124#define RH_SET_FEATURE 0x0300
125#define RH_SET_ADDRESS 0x0500
126#define RH_GET_DESCRIPTOR 0x0680
127#define RH_SET_DESCRIPTOR 0x0700
128#define RH_GET_CONFIGURATION 0x0880
129#define RH_SET_CONFIGURATION 0x0900
130#define RH_GET_STATE 0x0280
131#define RH_GET_INTERFACE 0x0A80
132#define RH_SET_INTERFACE 0x0B00
133#define RH_SYNC_FRAME 0x0C80
134/* Our Vendor Specific Request */
135#define RH_SET_EP 0x2000
136
137/* Hub port features */
138#define RH_PORT_CONNECTION 0x00
139#define RH_PORT_ENABLE 0x01
140#define RH_PORT_SUSPEND 0x02
141#define RH_PORT_OVER_CURRENT 0x03
142#define RH_PORT_RESET 0x04
143#define RH_PORT_POWER 0x08
144#define RH_PORT_LOW_SPEED 0x09
145#define RH_C_PORT_CONNECTION 0x10
146#define RH_C_PORT_ENABLE 0x11
147#define RH_C_PORT_SUSPEND 0x12
148#define RH_C_PORT_OVER_CURRENT 0x13
149#define RH_C_PORT_RESET 0x14
150
151/* Hub features */
152#define RH_C_HUB_LOCAL_POWER 0x00
153#define RH_C_HUB_OVER_CURRENT 0x01
154
155#define RH_DEVICE_REMOTE_WAKEUP 0x00
156#define RH_ENDPOINT_STALL 0x01
157
158/* Our Vendor Specific feature */
159#define RH_REMOVE_EP 0x00
160
161
162#define RH_ACK 0x01
163#define RH_REQ_ERR -1
164#define RH_NACK 0x00
165
166
167/* Transfer descriptor structure */
168typedef struct {
169 unsigned long link; /* next td/qh (LE)*/
170 unsigned long status; /* status of the td */
171 unsigned long info; /* Max Lenght / Endpoint / device address and PID */
172 unsigned long buffer; /* pointer to data buffer (LE) */
173 unsigned long dev_ptr; /* pointer to the assigned device (BE) */
174 unsigned long res[3]; /* reserved (TDs must be 8Byte aligned) */
175} uhci_td_t, *puhci_td_t;
176
177/* Queue Header structure */
178typedef struct {
179 unsigned long head; /* Next QH (LE)*/
180 unsigned long element; /* Queue element pointer (LE) */
181 unsigned long res[5]; /* reserved */
182 unsigned long dev_ptr; /* if 0 no tds have been assigned to this qh */
183} uhci_qh_t, *puhci_qh_t;
184
185struct virt_root_hub {
186 int devnum; /* Address of Root Hub endpoint */
187 int numports; /* number of ports */
188 int c_p_r[8]; /* C_PORT_RESET */
189};
190
191
192#endif /* _USB_UHCI_H_ */