| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) |
| 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_ZYNQMP_R5_H |
| 7 | #define __CONFIG_ZYNQMP_R5_H |
| 8 | |
| Tom Rini | 0613c36 | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 9 | #define CFG_EXTRA_ENV_SETTINGS |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 10 | |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 11 | /* Serial drivers */ |
| 12 | /* The following table includes the supported baudrates */ |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 13 | #define CFG_SYS_BAUDRATE_TABLE \ |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 14 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
| 15 | |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 16 | /* Boot configuration */ |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 17 | |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 18 | #define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
| 19 | #define CFG_SYS_INIT_RAM_SIZE 0x1000 |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 20 | |
| 21 | /* Extend size of kernel image for uncompression */ |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 22 | |
| Michal Simek | 1d6c54e | 2018-04-12 17:39:46 +0200 | [diff] [blame] | 23 | #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ |